8 Commits (master)
 

Author SHA1 Message Date
  klaute 92d4ca3a2e First working signal generator - the frequency shift is nonlinear. Second 1MHz PLL output clock added. ago%!(EXTRA string=1 year %s)
  klaute 90aab2d857 First test using a variable frequency output. ago%!(EXTRA string=1 year %s)
  klaute 9465338e77 Just saved the project. ago%!(EXTRA string=1 year %s)
  klaute 64d4d949ad First functional sin wave generator added. Also added a signal trap configuration file. ago%!(EXTRA string=1 year %s)
  klaute 06e40845d7 Wavegenerator works now - output frequency is 438 kHz. ago%!(EXTRA string=1 year %s)
  klaute fbd3c05dfe Counter VHDL implementation added. ago%!(EXTRA string=1 year %s)
  klaute edce407a82 PLL intern is 450 MHz. Output pins are not able to drive faster than 250MHz. ago%!(EXTRA string=1 year %s)
  klaute a34bcc531d Initial commit. ago%!(EXTRA string=1 year %s)