From 29a93cfda87a5c2ba38aeafdba058aaa538b6f78 Mon Sep 17 00:00:00 2001
From: klaute <klaute@klaute.de>
Date: Mon, 26 Sep 2016 13:03:52 +0200
Subject: [PATCH] The mathplotlib output modified to show multiple subplots. A
 new capacitor added to the schematics.

---
 pcb/TenaTesta_ZL1CVD.kicad_pcb |  34 +++++-
 pcb/TenaTesta_ZL1CVD.net       | 208 +++++++++++++++++----------------
 pcb/TenaTesta_ZL1CVD.sch       | 123 +++++++++++++------
 tools/meas.py                  |  57 ++++++---
 tools/test.py                  |  12 --
 5 files changed, 267 insertions(+), 167 deletions(-)
 delete mode 100644 tools/test.py

diff --git a/pcb/TenaTesta_ZL1CVD.kicad_pcb b/pcb/TenaTesta_ZL1CVD.kicad_pcb
index b084b66..946ec5b 100644
--- a/pcb/TenaTesta_ZL1CVD.kicad_pcb
+++ b/pcb/TenaTesta_ZL1CVD.kicad_pcb
@@ -1,14 +1,14 @@
 (kicad_pcb (version 4) (host pcbnew 4.0.2+dfsg1-2~bpo8+1-stable)
 
   (general
-    (links 55)
-    (no_connects 55)
+    (links 57)
+    (no_connects 57)
     (area 78.05188 66.6095 138.331334 151.666333)
     (thickness 1.6)
     (drawings 0)
     (tracks 7)
     (zones 0)
-    (modules 28)
+    (modules 29)
     (nets 42)
   )
 
@@ -1113,6 +1113,34 @@
     )
   )
 
+  (module Capacitors_ThroughHole:C_Disc_D3_P2.5 (layer F.Cu) (tedit 0) (tstamp 57E8C5B7)
+    (at 127.127 121.031)
+    (descr "Capacitor 3mm Disc, Pitch 2.5mm")
+    (tags Capacitor)
+    (path /57E8D2EB)
+    (fp_text reference C8 (at 1.25 -2.5) (layer F.SilkS)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_text value 100n (at 1.25 2.5) (layer F.Fab)
+      (effects (font (size 1 1) (thickness 0.15)))
+    )
+    (fp_line (start -0.9 -1.5) (end 3.4 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.4 -1.5) (end 3.4 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start 3.4 1.5) (end -0.9 1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.9 1.5) (end -0.9 -1.5) (layer F.CrtYd) (width 0.05))
+    (fp_line (start -0.25 -1.25) (end 2.75 -1.25) (layer F.SilkS) (width 0.15))
+    (fp_line (start 2.75 1.25) (end -0.25 1.25) (layer F.SilkS) (width 0.15))
+    (pad 1 thru_hole rect (at 0 0) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask F.SilkS)
+      (net 1 GND))
+    (pad 2 thru_hole circle (at 2.5 0) (size 1.3 1.3) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
+      (net 9 +5V))
+    (model Capacitors_ThroughHole.3dshapes/C_Disc_D3_P2.5.wrl
+      (at (xyz 0.0492126 0 0))
+      (scale (xyz 1 1 1))
+      (rotate (xyz 0 0 0))
+    )
+  )
+
   (segment (start 116.586 121.031) (end 116.586 120.5186) (width 0.25) (layer B.Cu) (net 1))
   (segment (start 129.159 77.978) (end 129.159 77.3835) (width 0.25) (layer B.Cu) (net 1))
   (segment (start 82.296 116.078) (end 82.677 116.459) (width 0.25) (layer B.Cu) (net 1))
diff --git a/pcb/TenaTesta_ZL1CVD.net b/pcb/TenaTesta_ZL1CVD.net
index 50e392d..07388db 100644
--- a/pcb/TenaTesta_ZL1CVD.net
+++ b/pcb/TenaTesta_ZL1CVD.net
@@ -1,7 +1,7 @@
 (export (version D)
   (design
-    (source /media/win/Users/klaute/dev/ham/TenaTesta/pcb/TenaTesta_ZL1CVD.sch)
-    (date "Sa 17 Sep 2016 19:54:43 CEST")
+    (source /media/win/Users/klaute/dev/ham/SWRMeter/pcb/TenaTesta_ZL1CVD.sch)
+    (date "Mo 26 Sep 2016 08:51:49 CEST")
     (tool "Eeschema 4.0.2+dfsg1-2~bpo8+1-stable")
     (sheet (number 1) (name /) (tstamps /)
       (title_block
@@ -182,7 +182,13 @@
       (footprint Buttons_Switches_ThroughHole:SW_PUSH_SMALL)
       (libsource (lib device) (part SW_PUSH))
       (sheetpath (names /) (tstamps /))
-      (tstamp 57D8B330)))
+      (tstamp 57D8B330))
+    (comp (ref C8)
+      (value 100n)
+      (footprint Capacitors_ThroughHole:C_Disc_D3_P2.5)
+      (libsource (lib device) (part C))
+      (sheetpath (names /) (tstamps /))
+      (tstamp 57E8D2EB)))
   (libparts
     (libpart (lib conn) (part BNC)
       (footprints
@@ -335,143 +341,145 @@
   (libraries
     (library (logical device)
       (uri /usr/share/kicad/library/device.lib))
-    (library (logical linear)
-      (uri /usr/share/kicad/library/linear.lib))
     (library (logical conn)
-      (uri /usr/share/kicad/library/conn.lib)))
+      (uri /usr/share/kicad/library/conn.lib))
+    (library (logical linear)
+      (uri /usr/share/kicad/library/linear.lib)))
   (nets
-    (net (code 1) (name /A0)
-      (node (ref U1) (pin 7))
-      (node (ref P5) (pin 12))
-      (node (ref R6) (pin 1))
-      (node (ref P2) (pin 1)))
-    (net (code 2) (name +5V)
-      (node (ref P4) (pin 7))
-      (node (ref C6) (pin 2))
-      (node (ref P5) (pin 4))
-      (node (ref U1) (pin 8)))
-    (net (code 3) (name GND)
-      (node (ref R5) (pin 2))
-      (node (ref P3) (pin 4))
-      (node (ref P5) (pin 2))
-      (node (ref R8) (pin 2))
+    (net (code 1) (name "Net-(P3-Pad5)")
+      (node (ref P3) (pin 5)))
+    (net (code 2) (name GND)
+      (node (ref U1) (pin 4))
+      (node (ref C5) (pin 1))
+      (node (ref C1) (pin 1))
+      (node (ref C3) (pin 1))
+      (node (ref P1) (pin 2))
+      (node (ref C7) (pin 2))
+      (node (ref C8) (pin 1))
+      (node (ref SW1) (pin 1))
+      (node (ref P4) (pin 6))
       (node (ref P6) (pin 1))
       (node (ref P6) (pin 3))
-      (node (ref SW1) (pin 1))
-      (node (ref C5) (pin 1))
-      (node (ref P1) (pin 2))
-      (node (ref C3) (pin 1))
-      (node (ref C1) (pin 1))
-      (node (ref U1) (pin 4))
+      (node (ref R5) (pin 2))
       (node (ref R1) (pin 2))
-      (node (ref C7) (pin 2))
-      (node (ref R10) (pin 1))
+      (node (ref R8) (pin 2))
       (node (ref R3) (pin 2))
-      (node (ref C6) (pin 1))
-      (node (ref P4) (pin 6)))
-    (net (code 4) (name "Net-(P3-Pad1)")
+      (node (ref R10) (pin 1))
+      (node (ref P5) (pin 2))
+      (node (ref P3) (pin 4))
+      (node (ref C6) (pin 1)))
+    (net (code 3) (name "Net-(P3-Pad1)")
       (node (ref P3) (pin 1)))
-    (net (code 5) (name "Net-(P3-Pad2)")
+    (net (code 4) (name "Net-(P3-Pad2)")
       (node (ref P3) (pin 2)))
-    (net (code 6) (name "Net-(P3-Pad3)")
+    (net (code 5) (name "Net-(P3-Pad3)")
       (node (ref P3) (pin 3)))
-    (net (code 7) (name "Net-(P3-Pad5)")
-      (node (ref P3) (pin 5)))
-    (net (code 8) (name "Net-(P3-Pad6)")
+    (net (code 6) (name "Net-(P3-Pad6)")
       (node (ref P3) (pin 6)))
-    (net (code 9) (name "Net-(P3-Pad7)")
+    (net (code 7) (name "Net-(P3-Pad7)")
       (node (ref P3) (pin 7)))
-    (net (code 10) (name "Net-(P3-Pad8)")
+    (net (code 8) (name "Net-(P3-Pad8)")
       (node (ref P3) (pin 8)))
-    (net (code 11) (name "Net-(P3-Pad9)")
+    (net (code 9) (name "Net-(P3-Pad9)")
       (node (ref P3) (pin 9)))
-    (net (code 12) (name "Net-(P3-Pad10)")
+    (net (code 10) (name "Net-(P3-Pad10)")
       (node (ref P3) (pin 10)))
-    (net (code 13) (name "Net-(P3-Pad11)")
+    (net (code 11) (name "Net-(P3-Pad11)")
       (node (ref P3) (pin 11)))
-    (net (code 14) (name "Net-(P3-Pad12)")
+    (net (code 12) (name "Net-(P3-Pad12)")
       (node (ref P3) (pin 12)))
-    (net (code 15) (name "Net-(P3-Pad13)")
+    (net (code 13) (name "Net-(P3-Pad13)")
       (node (ref P3) (pin 13)))
-    (net (code 16) (name "Net-(P3-Pad14)")
+    (net (code 14) (name "Net-(P3-Pad14)")
       (node (ref P3) (pin 14)))
-    (net (code 17) (name /SDA)
-      (node (ref P4) (pin 5))
-      (node (ref P5) (pin 8)))
-    (net (code 18) (name /CLK0)
-      (node (ref P4) (pin 1))
-      (node (ref P6) (pin 2))
-      (node (ref C4) (pin 1)))
+    (net (code 15) (name "Net-(P3-Pad15)")
+      (node (ref P3) (pin 15)))
+    (net (code 16) (name "Net-(P5-Pad1)")
+      (node (ref P5) (pin 1)))
+    (net (code 17) (name /RESET)
+      (node (ref P5) (pin 3))
+      (node (ref SW1) (pin 2)))
+    (net (code 18) (name "Net-(P5-Pad5)")
+      (node (ref P5) (pin 5)))
     (net (code 19) (name /CLK1)
       (node (ref P4) (pin 2)))
     (net (code 20) (name /CLK2)
       (node (ref P4) (pin 3)))
     (net (code 21) (name /SCL)
-      (node (ref P4) (pin 4))
-      (node (ref P5) (pin 7)))
-    (net (code 22) (name "Net-(P3-Pad15)")
-      (node (ref P3) (pin 15)))
-    (net (code 23) (name "Net-(R1-Pad1)")
+      (node (ref P5) (pin 7))
+      (node (ref P4) (pin 4)))
+    (net (code 22) (name /SDA)
+      (node (ref P4) (pin 5))
+      (node (ref P5) (pin 8)))
+    (net (code 23) (name +5V)
+      (node (ref P5) (pin 4))
+      (node (ref P4) (pin 7))
+      (node (ref C6) (pin 2))
+      (node (ref C8) (pin 2))
+      (node (ref U1) (pin 8)))
+    (net (code 24) (name "Net-(P5-Pad6)")
+      (node (ref P5) (pin 6)))
+    (net (code 25) (name /CLK0)
+      (node (ref P6) (pin 2))
+      (node (ref C4) (pin 1))
+      (node (ref P4) (pin 1)))
+    (net (code 26) (name "Net-(C7-Pad1)")
+      (node (ref C7) (pin 1))
+      (node (ref P5) (pin 13)))
+    (net (code 27) (name "Net-(P5-Pad9)")
+      (node (ref P5) (pin 9)))
+    (net (code 28) (name "Net-(P5-Pad10)")
+      (node (ref P5) (pin 10)))
+    (net (code 29) (name "Net-(P5-Pad14)")
+      (node (ref P5) (pin 14)))
+    (net (code 30) (name "Net-(P5-Pad15)")
+      (node (ref P5) (pin 15)))
+    (net (code 31) (name /A1)
+      (node (ref P5) (pin 11))
+      (node (ref U1) (pin 1))
+      (node (ref R2) (pin 1))
+      (node (ref P2) (pin 2)))
+    (net (code 32) (name "Net-(R1-Pad1)")
       (node (ref U1) (pin 2))
-      (node (ref R1) (pin 1))
-      (node (ref R2) (pin 2)))
-    (net (code 24) (name "Net-(R5-Pad1)")
+      (node (ref R2) (pin 2))
+      (node (ref R1) (pin 1)))
+    (net (code 33) (name "Net-(R5-Pad1)")
       (node (ref R6) (pin 2))
       (node (ref R5) (pin 1))
       (node (ref U1) (pin 6)))
-    (net (code 25) (name /A1)
-      (node (ref P5) (pin 11))
-      (node (ref P2) (pin 2))
-      (node (ref R2) (pin 1))
-      (node (ref U1) (pin 1)))
-    (net (code 26) (name /RESET)
-      (node (ref P5) (pin 3))
-      (node (ref SW1) (pin 2)))
-    (net (code 27) (name "Net-(P5-Pad15)")
-      (node (ref P5) (pin 15)))
-    (net (code 28) (name "Net-(P5-Pad1)")
-      (node (ref P5) (pin 1)))
-    (net (code 29) (name "Net-(P5-Pad5)")
-      (node (ref P5) (pin 5)))
-    (net (code 30) (name "Net-(P5-Pad6)")
-      (node (ref P5) (pin 6)))
-    (net (code 31) (name "Net-(P5-Pad9)")
-      (node (ref P5) (pin 9)))
-    (net (code 32) (name "Net-(P5-Pad10)")
-      (node (ref P5) (pin 10)))
-    (net (code 33) (name "Net-(P5-Pad14)")
-      (node (ref P5) (pin 14)))
-    (net (code 34) (name "Net-(C7-Pad1)")
-      (node (ref C7) (pin 1))
-      (node (ref P5) (pin 13)))
+    (net (code 34) (name /A0)
+      (node (ref U1) (pin 7))
+      (node (ref P2) (pin 1))
+      (node (ref R6) (pin 1))
+      (node (ref P5) (pin 12)))
     (net (code 35) (name "Net-(C2-Pad2)")
-      (node (ref R7) (pin 2))
       (node (ref P1) (pin 1))
+      (node (ref R7) (pin 2))
       (node (ref C2) (pin 2)))
     (net (code 36) (name "Net-(C4-Pad2)")
-      (node (ref R9) (pin 2))
+      (node (ref R7) (pin 1))
       (node (ref C4) (pin 2))
-      (node (ref R7) (pin 1)))
+      (node (ref R9) (pin 2)))
     (net (code 37) (name "Net-(C5-Pad2)")
-      (node (ref C5) (pin 2))
+      (node (ref R11) (pin 2))
       (node (ref D2) (pin 1))
-      (node (ref R11) (pin 2)))
+      (node (ref C5) (pin 2)))
     (net (code 38) (name "Net-(C1-Pad2)")
-      (node (ref U1) (pin 3))
+      (node (ref R4) (pin 1))
       (node (ref R3) (pin 1))
-      (node (ref C1) (pin 2))
-      (node (ref R4) (pin 1)))
+      (node (ref U1) (pin 3))
+      (node (ref C1) (pin 2)))
     (net (code 39) (name "Net-(C3-Pad2)")
-      (node (ref R8) (pin 1))
-      (node (ref R11) (pin 1))
+      (node (ref U1) (pin 5))
       (node (ref C3) (pin 2))
-      (node (ref U1) (pin 5)))
+      (node (ref R8) (pin 1))
+      (node (ref R11) (pin 1)))
     (net (code 40) (name "Net-(C2-Pad1)")
-      (node (ref R4) (pin 2))
       (node (ref D1) (pin 1))
-      (node (ref C2) (pin 1)))
+      (node (ref C2) (pin 1))
+      (node (ref R4) (pin 2)))
     (net (code 41) (name "Net-(D1-Pad2)")
+      (node (ref R10) (pin 2))
       (node (ref D1) (pin 2))
-      (node (ref D2) (pin 2))
       (node (ref R9) (pin 1))
-      (node (ref R10) (pin 2)))))
\ No newline at end of file
+      (node (ref D2) (pin 2)))))
\ No newline at end of file
diff --git a/pcb/TenaTesta_ZL1CVD.sch b/pcb/TenaTesta_ZL1CVD.sch
index c9ce228..fe6b935 100644
--- a/pcb/TenaTesta_ZL1CVD.sch
+++ b/pcb/TenaTesta_ZL1CVD.sch
@@ -266,10 +266,10 @@ $EndComp
 Wire Wire Line
 	5150 2250 4200 2250
 $Comp
-L GND #PWR01
+L GND #PWR8
 U 1 1 57D82504
 P 5300 2550
-F 0 "#PWR01" H 5300 2300 50  0001 C CNN
+F 0 "#PWR8" H 5300 2300 50  0001 C CNN
 F 1 "GND" H 5300 2400 50  0000 C CNN
 F 2 "" H 5300 2550 50  0000 C CNN
 F 3 "" H 5300 2550 50  0000 C CNN
@@ -335,10 +335,10 @@ Connection ~ 2550 3000
 Wire Wire Line
 	2550 3950 2550 3600
 $Comp
-L GND #PWR02
+L GND #PWR3
 U 1 1 57D83353
 P 3450 3700
-F 0 "#PWR02" H 3450 3450 50  0001 C CNN
+F 0 "#PWR3" H 3450 3450 50  0001 C CNN
 F 1 "GND" H 3450 3550 50  0000 C CNN
 F 2 "" H 3450 3700 50  0000 C CNN
 F 3 "" H 3450 3700 50  0000 C CNN
@@ -346,10 +346,10 @@ F 3 "" H 3450 3700 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR03
+L GND #PWR1
 U 1 1 57D833E2
 P 2000 3700
-F 0 "#PWR03" H 2000 3450 50  0001 C CNN
+F 0 "#PWR1" H 2000 3450 50  0001 C CNN
 F 1 "GND" H 2000 3550 50  0000 C CNN
 F 2 "" H 2000 3700 50  0000 C CNN
 F 3 "" H 2000 3700 50  0000 C CNN
@@ -371,10 +371,10 @@ Wire Wire Line
 	4150 4950 3650 4950
 Connection ~ 4150 4950
 $Comp
-L GND #PWR04
+L GND #PWR7
 U 1 1 57D83F2B
 P 5200 5350
-F 0 "#PWR04" H 5200 5100 50  0001 C CNN
+F 0 "#PWR7" H 5200 5100 50  0001 C CNN
 F 1 "GND" H 5200 5200 50  0000 C CNN
 F 2 "" H 5200 5350 50  0000 C CNN
 F 3 "" H 5200 5350 50  0000 C CNN
@@ -382,10 +382,10 @@ F 3 "" H 5200 5350 50  0000 C CNN
 	-1   0    0    -1  
 $EndComp
 $Comp
-L GND #PWR05
+L GND #PWR4
 U 1 1 57D84180
 P 3950 5350
-F 0 "#PWR05" H 3950 5100 50  0001 C CNN
+F 0 "#PWR4" H 3950 5100 50  0001 C CNN
 F 1 "GND" H 3950 5200 50  0000 C CNN
 F 2 "" H 3950 5350 50  0000 C CNN
 F 3 "" H 3950 5350 50  0000 C CNN
@@ -410,10 +410,10 @@ Wire Wire Line
 	4800 5650 4800 5750
 Connection ~ 4800 5750
 $Comp
-L +5V #PWR06
+L +5V #PWR2
 U 1 1 57D84814
 P 3150 5150
-F 0 "#PWR06" H 3150 5000 50  0001 C CNN
+F 0 "#PWR2" H 3150 5000 50  0001 C CNN
 F 1 "+5V" H 3150 5290 50  0000 C CNN
 F 2 "" H 3150 5150 50  0000 C CNN
 F 3 "" H 3150 5150 50  0000 C CNN
@@ -446,10 +446,10 @@ Wire Wire Line
 Wire Wire Line
 	9900 2050 10000 2050
 $Comp
-L GND #PWR07
+L GND #PWR18
 U 1 1 57D854FE
 P 9900 2150
-F 0 "#PWR07" H 9900 1900 50  0001 C CNN
+F 0 "#PWR18" H 9900 1900 50  0001 C CNN
 F 1 "GND" H 9900 2000 50  0000 C CNN
 F 2 "" H 9900 2150 50  0000 C CNN
 F 3 "" H 9900 2150 50  0000 C CNN
@@ -485,10 +485,10 @@ Wire Wire Line
 Wire Wire Line
 	7800 2300 8100 2300
 $Comp
-L +5V #PWR08
+L +5V #PWR12
 U 1 1 57D85B32
 P 7800 2300
-F 0 "#PWR08" H 7800 2150 50  0001 C CNN
+F 0 "#PWR12" H 7800 2150 50  0001 C CNN
 F 1 "+5V" H 7800 2440 50  0000 C CNN
 F 2 "" H 7800 2300 50  0000 C CNN
 F 3 "" H 7800 2300 50  0000 C CNN
@@ -496,10 +496,10 @@ F 3 "" H 7800 2300 50  0000 C CNN
 	0    -1   -1   0   
 $EndComp
 $Comp
-L GND #PWR09
+L GND #PWR14
 U 1 1 57D85C77
 P 8000 2400
-F 0 "#PWR09" H 8000 2150 50  0001 C CNN
+F 0 "#PWR14" H 8000 2150 50  0001 C CNN
 F 1 "GND" H 8000 2250 50  0000 C CNN
 F 2 "" H 8000 2400 50  0000 C CNN
 F 3 "" H 8000 2400 50  0000 C CNN
@@ -522,10 +522,10 @@ F 3 "" H 7350 2050 50  0000 C CNN
 	-1   0    0    1   
 $EndComp
 $Comp
-L +5V #PWR010
+L +5V #PWR10
 U 1 1 57D85E0F
 P 7350 1800
-F 0 "#PWR010" H 7350 1650 50  0001 C CNN
+F 0 "#PWR10" H 7350 1650 50  0001 C CNN
 F 1 "+5V" H 7350 1940 50  0000 C CNN
 F 2 "" H 7350 1800 50  0000 C CNN
 F 3 "" H 7350 1800 50  0000 C CNN
@@ -533,10 +533,10 @@ F 3 "" H 7350 1800 50  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L GND #PWR011
+L GND #PWR11
 U 1 1 57D85E65
 P 7350 2300
-F 0 "#PWR011" H 7350 2050 50  0001 C CNN
+F 0 "#PWR11" H 7350 2050 50  0001 C CNN
 F 1 "GND" H 7350 2150 50  0000 C CNN
 F 2 "" H 7350 2300 50  0000 C CNN
 F 3 "" H 7350 2300 50  0000 C CNN
@@ -560,10 +560,10 @@ SDA
 Wire Wire Line
 	8000 4050 8200 4050
 $Comp
-L GND #PWR012
+L GND #PWR15
 U 1 1 57D86AF6
 P 8000 4050
-F 0 "#PWR012" H 8000 3800 50  0001 C CNN
+F 0 "#PWR15" H 8000 3800 50  0001 C CNN
 F 1 "GND" H 8000 3900 50  0000 C CNN
 F 2 "" H 8000 4050 50  0000 C CNN
 F 3 "" H 8000 4050 50  0000 C CNN
@@ -571,10 +571,10 @@ F 3 "" H 8000 4050 50  0000 C CNN
 	0    1    1    0   
 $EndComp
 $Comp
-L +5V #PWR013
+L +5V #PWR17
 U 1 1 57D86BE1
 P 9500 4050
-F 0 "#PWR013" H 9500 3900 50  0001 C CNN
+F 0 "#PWR17" H 9500 3900 50  0001 C CNN
 F 1 "+5V" H 9500 4190 50  0000 C CNN
 F 2 "" H 9500 4050 50  0000 C CNN
 F 3 "" H 9500 4050 50  0000 C CNN
@@ -584,10 +584,10 @@ $EndComp
 Wire Wire Line
 	9300 4050 9500 4050
 $Comp
-L GND #PWR014
+L GND #PWR16
 U 1 1 57D86CAF
 P 9500 3850
-F 0 "#PWR014" H 9500 3600 50  0001 C CNN
+F 0 "#PWR16" H 9500 3600 50  0001 C CNN
 F 1 "GND" H 9500 3700 50  0000 C CNN
 F 2 "" H 9500 3850 50  0000 C CNN
 F 3 "" H 9500 3850 50  0000 C CNN
@@ -658,10 +658,10 @@ $EndComp
 Wire Wire Line
 	9300 4950 9600 4950
 $Comp
-L GND #PWR015
+L GND #PWR19
 U 1 1 57D88248
 P 10000 4950
-F 0 "#PWR015" H 10000 4700 50  0001 C CNN
+F 0 "#PWR19" H 10000 4700 50  0001 C CNN
 F 1 "GND" H 10000 4800 50  0000 C CNN
 F 2 "" H 10000 4950 50  0000 C CNN
 F 3 "" H 10000 4950 50  0000 C CNN
@@ -671,10 +671,10 @@ $EndComp
 Wire Wire Line
 	9900 4950 10000 4950
 $Comp
-L +5V #PWR016
+L +5V #PWR6
 U 1 1 57D888AD
 P 4400 5150
-F 0 "#PWR016" H 4400 5000 50  0001 C CNN
+F 0 "#PWR6" H 4400 5000 50  0001 C CNN
 F 1 "+5V" H 4400 5290 50  0000 C CNN
 F 2 "" H 4400 5150 50  0000 C CNN
 F 3 "" H 4400 5150 50  0000 C CNN
@@ -728,10 +728,10 @@ Si5351 breakout board
 Text Notes 5400 2050 2    60   ~ 0
 ANT
 $Comp
-L GND #PWR017
+L GND #PWR5
 U 1 1 57D8AC18
 P 4250 4200
-F 0 "#PWR017" H 4250 3950 50  0001 C CNN
+F 0 "#PWR5" H 4250 3950 50  0001 C CNN
 F 1 "GND" H 4250 4050 50  0000 C CNN
 F 2 "" H 4250 4200 50  0000 C CNN
 F 3 "" H 4250 4200 50  0000 C CNN
@@ -739,10 +739,10 @@ F 3 "" H 4250 4200 50  0000 C CNN
 	0    -1   1    0   
 $EndComp
 $Comp
-L GND #PWR018
+L GND #PWR9
 U 1 1 57D8ACE7
 P 5500 4200
-F 0 "#PWR018" H 5500 3950 50  0001 C CNN
+F 0 "#PWR9" H 5500 3950 50  0001 C CNN
 F 1 "GND" H 5500 4050 50  0000 C CNN
 F 2 "" H 5500 4200 50  0000 C CNN
 F 3 "" H 5500 4200 50  0000 C CNN
@@ -769,10 +769,10 @@ Wire Wire Line
 Text Label 8850 6150 0    60   ~ 0
 RESET
 $Comp
-L GND #PWR019
+L GND #PWR13
 U 1 1 57D8B741
 P 7900 6150
-F 0 "#PWR019" H 7900 5900 50  0001 C CNN
+F 0 "#PWR13" H 7900 5900 50  0001 C CNN
 F 1 "GND" H 7900 6000 50  0000 C CNN
 F 2 "" H 7900 6150 50  0000 C CNN
 F 3 "" H 7900 6150 50  0000 C CNN
@@ -787,4 +787,51 @@ Text Notes 8000 5950 0    60   ~ 0
 Arduino reset
 Text Notes 4300 2050 2    60   ~ 0
 Wheatstone impedance bridge
+Wire Notes Line
+	8600 5200 8900 5200
+Wire Notes Line
+	8900 5200 8900 5500
+Wire Notes Line
+	8900 5500 8600 5500
+Wire Notes Line
+	8600 5500 8600 5200
+Text Notes 8600 5450 0    99   ~ 0
+USB
+$Comp
+L C C8
+U 1 1 57E8D2EB
+P 10650 4350
+F 0 "C8" H 10675 4450 50  0000 L CNN
+F 1 "100n" H 10675 4250 50  0000 L CNN
+F 2 "Capacitors_ThroughHole:C_Disc_D3_P2.5" H 10688 4200 50  0001 C CNN
+F 3 "" H 10650 4350 50  0000 C CNN
+	1    10650 4350
+	-1   0    0    1   
+$EndComp
+$Comp
+L +5V #PWR20
+U 1 1 57E8D54F
+P 10650 4100
+F 0 "#PWR20" H 10650 3950 50  0001 C CNN
+F 1 "+5V" H 10650 4240 50  0000 C CNN
+F 2 "" H 10650 4100 50  0000 C CNN
+F 3 "" H 10650 4100 50  0000 C CNN
+	1    10650 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L GND #PWR21
+U 1 1 57E8D5B4
+P 10650 4600
+F 0 "#PWR21" H 10650 4350 50  0001 C CNN
+F 1 "GND" H 10650 4450 50  0000 C CNN
+F 2 "" H 10650 4600 50  0000 C CNN
+F 3 "" H 10650 4600 50  0000 C CNN
+	1    10650 4600
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	10650 4100 10650 4200
+Wire Wire Line
+	10650 4600 10650 4500
 $EndSCHEMATC
diff --git a/tools/meas.py b/tools/meas.py
index c47da29..1c16665 100644
--- a/tools/meas.py
+++ b/tools/meas.py
@@ -9,6 +9,7 @@ import copy
 import binascii
 import matplotlib.pyplot as plt
 import math
+import operator
 
 ###############################################################################
 
@@ -499,7 +500,9 @@ if __name__ == "__main__":
           meas_freq = []
           meas_ratio = []
           meas_r = []
-          meas_p = []
+          meas_a0 = []
+          meas_a1 = []
+          meas_ratio_f = {}
 
           min_vswr = [ 10, 0 ] # the default VSWR is 10 and the default freq is 0]
 
@@ -511,6 +514,9 @@ if __name__ == "__main__":
               meas_freq.append(m[0])
               vswr = 0
 
+              meas_a0.append(m[1])
+              meas_a1.append(m[2])
+
               if m[1] > 0 and m[2] > 0:
                 if m[1] > m[2]:
                   vswr = (1.0 * m[1] / m[2])
@@ -525,6 +531,8 @@ if __name__ == "__main__":
                 vswr = 1
                 meas_ratio.append(1)
 
+              meas_ratio_f[m[0]] = vswr
+
               if vswr < min_vswr[0]:
                 min_vswr[0] = vswr
                 min_vswr[1] = m[0] # the frequency
@@ -533,12 +541,7 @@ if __name__ == "__main__":
               r = 50.0 * vswr
               meas_r.append(r)
 
-              # P = meas_data[0] * 5V ^ 2 / r
-              if r > 0:
-                meas_p.append(math.pow(i, 2) * r)
-              else:
-                meas_p.append(0)
-
+          #####
           if args.output_file != None:
             FILE = open(args.output_file, "w")
             FILE.write("freqency;ratio;impedance;watt;drive;a0;a1\n")
@@ -549,18 +552,44 @@ if __name__ == "__main__":
             FILE.close()
             print "Output file " + args.output_file + " written."
 
-          if args.show_graph == True:
-            lv, = plt.plot(meas_freq, meas_ratio, label='VSWR')
-            lr, = plt.plot(meas_freq, meas_r, label='Impedance')
-            lw, = plt.plot(meas_freq, meas_p, label='Watt')
+          print "First minimum VSWR " + str(min_vswr[0]) + " found at freqency " + user_friendly_freq(min_vswr[1])
 
-            plt.legend(handles=[lv, lr, lw])
+          #####
+          if args.show_graph == True:
+
+            f, axarr = plt.subplots(3, sharex=True)
+
+            f.canvas.set_window_title("SWR meter measurement results")
+
+            vswr_marker = []
+            i = 0
+            old = 1000
+            #for r in sorted(meas_ratio_f.items(), key=operator.itemgetter(1)):
+            for r in sorted(meas_ratio):
+              #vswr_marker.append(r[0])
+              vswr_marker.append(r)
+              if r > old:
+                i += 1
+              old = r
+              if i == 5:
+                break
+
+            lv, = axarr[0].plot(meas_freq, meas_ratio, label='VSWR', markevery=vswr_marker, markersize=5, marker="o", markerfacecolor="g")
+            lr, = axarr[1].plot(meas_freq, meas_r, label='impedance')
+            la0, = axarr[2].plot(meas_freq, meas_a0, label='a0')
+            la1, = axarr[2].plot(meas_freq, meas_a1, label='a1')
+
+            axarr[0].legend(handles=[lv])
+            axarr[0].scatter(meas_freq, meas_ratio, 1)
+            axarr[1].legend(handles=[lr])
+            axarr[1].scatter(meas_freq, meas_r, 1)
+            axarr[2].legend(handles=[la0, la1])
+            axarr[2].set_ylim([0, 1024])
 
             print "Please close the mathplot window to exit..."
+            plt.grid()
             plt.show()
 
-          print "First minimum VSWR " + str(min_vswr[0]) + " found at freqency " + user_friendly_freq(min_vswr[1])
-
         else:
           print "err: unknown type 0x%02x" % (e[1])
           break
diff --git a/tools/test.py b/tools/test.py
deleted file mode 100644
index db64c9d..0000000
--- a/tools/test.py
+++ /dev/null
@@ -1,12 +0,0 @@
-import serial, sys
-port = "/dev/ttyUSB0"
-baudrate = 115200
-ser = serial.Serial(port,baudrate,timeout=0.001)
-while True:
-    ser.write(bytearray([0x3c, 0x3e, 0x10, 0x0d, 0x0a]))
-
-    if ser.inWaiting() > 0:
-      data = list(ser.read(64))
-      print data
-
-    sys.stdout.flush()