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Added missing frequency set calls to the rf generator output.

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klaute 2016-09-28 15:14:57 +02:00
parent ac9f77d8d5
commit 7a5140b313
1 changed files with 3 additions and 0 deletions
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3
firmware/command_ctrl.ino
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@ -323,16 +323,19 @@ void cc_enableClk(void)
Serial.write(MSG_SOM2); Serial.write(MSG_SOM2);
if (cc_read_data[0] == SI5351_CLK0) if (cc_read_data[0] == SI5351_CLK0)
{ {
si5351.set_freq((uint64_t)start_freq * 100, SI5351_PLL_FIXED, SI5351_CLK0);
si5351.output_enable(SI5351_CLK0, 1); // enable clock output 0 si5351.output_enable(SI5351_CLK0, 1); // enable clock output 0
Serial.write(MSG_TYPE_ANSWER_OK); Serial.write(MSG_TYPE_ANSWER_OK);
} }
else if (cc_read_data[0] == SI5351_CLK1) else if (cc_read_data[0] == SI5351_CLK1)
{ {
si5351.set_freq((uint64_t)start_freq * 100, SI5351_PLL_FIXED, SI5351_CLK1);
si5351.output_enable(SI5351_CLK1, 1); // enable clock output 1 si5351.output_enable(SI5351_CLK1, 1); // enable clock output 1
Serial.write(MSG_TYPE_ANSWER_OK); Serial.write(MSG_TYPE_ANSWER_OK);
} }
else if (cc_read_data[0] == SI5351_CLK2) else if (cc_read_data[0] == SI5351_CLK2)
{ {
si5351.set_freq((uint64_t)start_freq * 100, SI5351_PLL_FIXED, SI5351_CLK2);
si5351.output_enable(SI5351_CLK2, 1); // enable clock output 2 si5351.output_enable(SI5351_CLK2, 1); // enable clock output 2
Serial.write(MSG_TYPE_ANSWER_OK); Serial.write(MSG_TYPE_ANSWER_OK);
} else { } else {