395 lines
12 KiB
C
Executable file
395 lines
12 KiB
C
Executable file
/*! \page License
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* Copyright (C) 2009, H&D Wireless AB All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of H&D Wireless AB may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY H&D WIRELESS AB ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
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* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <gpio.h>
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#include <intc.h>
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#include <string.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <wl_spi.h>
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#include <printf-stdarg.h>
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#include <board_init.h>
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#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
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__attribute__((__interrupt__)) void avr32_irq_handler(void);
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void owl_spi_mdelay(uint32_t ms);
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int owl_spi_init(U8 *flags)
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{
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#ifdef _ASSERT_ENABLE_ /* To silence warning if Assert() macro is empty */
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volatile avr32_pm_t *pm = &AVR32_PM;
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#endif
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volatile avr32_spi_t *spi = &WL_SPI;
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#if WL_SPI_CS == 1
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volatile avr32_spi_csr1_t* CSR = &spi->CSR1;
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#elif WL_SPI_CS == 2
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volatile avr32_spi_csr2_t* CSR = &spi->CSR2;
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#elif WL_SPI_CS == 3
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volatile avr32_spi_csr3_t* CSR = &spi->CSR3;
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#elif SPI_CS == 0
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volatile avr32_spi_csr0_t* CSR = &spi->CSR0;
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#endif
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#ifndef WITH_NO_DMA
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volatile avr32_pdca_channel_t *pdca_tx = &AVR32_PDCA.channel[0];
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volatile avr32_pdca_channel_t *pdca_rx = &AVR32_PDCA.channel[1];
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#endif
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#ifndef WL_IRQ_PIN
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*flags = SPI_FLAG_POLL;
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#else
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*flags = 0;
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#endif
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#ifdef WL_IRQ_PIN
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/* input, irq */
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gpio_enable_gpio_pin(WL_IRQ_PIN);
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gpio_enable_pin_pull_up(WL_IRQ_PIN);
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#endif
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//#ifdef WL_RESET_PIN
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// /* reset pin */
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// gpio_enable_gpio_pin(WL_RESET_PIN);
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// gpio_set_gpio_pin(WL_RESET_PIN);
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//#endif
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#ifdef WL_POWER_PIN
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/* power off the device */
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gpio_enable_gpio_pin(WL_POWER_PIN);
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gpio_set_gpio_pin(WL_POWER_PIN);
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#endif
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#ifdef WL_SHUTDOWN_PIN
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gpio_enable_gpio_pin(WL_SHUTDOWN_PIN);
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#ifdef WL_NO_INTERNAL_RESET /* never defined for SPB104/SPB105 */
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gpio_clr_gpio_pin(WL_SHUTDOWN_PIN);
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#endif
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#ifdef WL_EXTERNAL_RESET
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gpio_enable_gpio_pin(WL_RESET_PIN);
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#endif
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#endif /* WL_SHUTDOWN_PIN */
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#ifdef WL_POWER_PIN
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/* power on the device */
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gpio_clr_gpio_pin(WL_POWER_PIN);
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#endif
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#ifdef WL_SHUTDOWN_PIN
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#ifdef WL_NO_INTERNAL_RESET /* never defined for SPB104/SPB105 */
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owl_spi_mdelay(5);
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gpio_set_gpio_pin(WL_SHUTDOWN_PIN);
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#elif WL_EXTERNAL_RESET
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owl_spi_mdelay(5);
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gpio_set_gpio_pin(WL_SHUTDOWN_PIN);
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owl_spi_mdelay(20);
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//delay_ms(10); //2ms
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/* reset pin */
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gpio_set_gpio_pin(WL_RESET_PIN);
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#else
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/* The shutdown pin will go high once the device is powered */
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{
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#define SHUTDOWN_TIMEOUT 350
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uint32_t shutdown_timer = 0;
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while (gpio_get_pin_value(WL_SHUTDOWN_PIN) == 0) {
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if (shutdown_timer > SHUTDOWN_TIMEOUT)
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{
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printk("Timeout WL Shutdown\n");
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return -1;
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}
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owl_spi_mdelay(5);
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shutdown_timer += 5;
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}
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}
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#endif /* WL_NO_INTERNAL_RESET */
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#else
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/* We need to make a guess about the time needed to power the device,
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* this will depend on the hardware design.
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*/
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owl_spi_mdelay(5);
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#endif /* WL_SHUTDOWN_PIN */
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/* Note: SPI0 clock enabled at reset in pm->pbamask (see 13.6.3) */
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Assert(pm->pbamask & (1 << 5));
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/* Note: GPIO clock enabled at reset in pm->pbamask (see 13.6.3) */
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Assert(pm->pbamask & (1 << 1));
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#ifdef WL_IRQ_PIN
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/* 22.4.7: "In every port there are four interrupt lines
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* connected to the interrupt controller. Every eigth
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* interrupts in the port are ored together to form an
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* interrupt line."
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*
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* WL_IRQ_# = (WL_IRQ_PIN / 32) * 4 + (WL_IRQ_PIN / 8) % 4
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* 62 => 1 * 4 + 3 = 7
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*/
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INTC_register_interrupt(&avr32_irq_handler, WL_IRQ, AVR32_INTC_INT0);
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#endif
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#ifndef WITH_NO_DMA
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INTC_register_interrupt(&avr32_irq_handler, AVR32_PDCA_IRQ_0,
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AVR32_INTC_INT0);
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INTC_register_interrupt(&avr32_irq_handler, AVR32_PDCA_IRQ_1,
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AVR32_INTC_INT0);
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pdca_tx->IER.terr = 1;
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pdca_rx->IER.terr = 1;
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#endif
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#ifdef WL_SPI_CLOCK_DIVIDER
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CSR->scbr = WL_SPI_CLOCK_DIVIDER;
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#else
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CSR->scbr = 2;
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#endif
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/* Use max width of TDR register, 16 bit transfers */
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CSR->bits = 0x8;
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/* Make sure that we can hold CS low until transfer is completed, e.g
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* LASTXFER is set in TDR.
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*/
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CSR->csaat = 1;
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/* NRG component requires clock polarity high */
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CSR->cpol = 1;
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#ifdef WL_IRQ_PIN
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/* make sure to clear any pending bits in ifr here. */
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gpio_clear_pin_interrupt_flag(WL_IRQ_PIN);
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#endif
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return 0;
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}
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#ifndef WITH_NO_DMA
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static void dma_txrx(const U8* in, U8* out, U16 len)
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{
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volatile avr32_pdca_channel_t *pdca_tx = &AVR32_PDCA.channel[0];
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volatile avr32_pdca_channel_t *pdca_rx = &AVR32_PDCA.channel[1];
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/* setup tx */
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pdca_tx->mar = (U32) in;
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pdca_tx->PSR.pid = WL_PDCA_PID_TX;
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pdca_tx->tcr = len / 2;
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pdca_tx->MR.size = 1; /* 2-byte */
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pdca_tx->IER.trc = 1;
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/* setup rx */
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pdca_rx->mar = (U32) out;
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pdca_rx->PSR.pid = WL_PDCA_PID_RX;
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pdca_rx->tcr = len / 2;
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pdca_rx->MR.size = 1; /* 2-byte */
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pdca_rx->IER.trc = 1;
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/* start dma's. for some reason rx must be started prior to tx */
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pdca_rx->CR.ten = 1;
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pdca_tx->CR.ten = 1;
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/* blocking wait until transfer is completed */
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while (!(pdca_tx->ISR.trc && pdca_rx->ISR.trc));
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}
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#endif
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/* access data using byte pointers since we might get unaligned
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* data from lwip. The cpu will issue a data abort if we try
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* to access data which is not properly aligned. See data sheet.
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*
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* Note that fifo_txrx() doesn't handle the case where len is not a
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* multiple of two bytes properly.
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*
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* However, there is no actual case where len is odd at the same time
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* as the "out" pointer is non-NULL; therefore I think that in practice,
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* we'll not write beyond the end of the "out" array.
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*
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* The extra unknown byte fetched from the in pointer will be discarded
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* by the device since a length field included in the packet header will inform
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* the device of the actual number of valid bytes (this implementation is
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* kind of hidden inside the library).
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*/
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static void fifo_txrx(const U8 *in, U8* out, U16 len)
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{
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volatile avr32_spi_t *spi = &WL_SPI;
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UnionCPtr in_ptr;
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UnionPtr out_ptr;
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U32 sr;
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Assert(len);
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in_ptr.u8ptr = in;
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out_ptr.u8ptr = out;
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while (len) {
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U16 rdr;
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union {
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avr32_spi_tdr_t TDR;
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U32 tdr;
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} reg = { { 0 } };
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while (!spi->SR.tdre);
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while (!spi->SR.txempty);
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/* prepare tx data register contents */
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if (in_ptr.u8ptr) {
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reg.TDR.td |= (in_ptr.u8ptr[0] << 8) | in_ptr.u8ptr[1];
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in_ptr.u16ptr++;
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}
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else
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reg.TDR.td |= 0xffff;
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/* perform tx */
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spi->tdr = reg.tdr;
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/* wait until rx is ready */
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while (!spi->SR.rdrf);
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/* fetch rx data */
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rdr = spi->RDR.rd;
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if (out_ptr.u8ptr) {
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out_ptr.u8ptr[0] = (rdr >> 8) & 0xff;
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out_ptr.u8ptr[1] = rdr & 0xff;
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out_ptr.u16ptr++;
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}
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if (len >= 2)
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len -= 2;
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else
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len = 0;
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}
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sr = spi->sr;
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Assert(!(sr & AVR32_SPI_SR_OVRES_MASK));
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Assert(!(sr & AVR32_SPI_SR_MODF_MASK));
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}
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void owl_spi_txrx(const U8 *in, U8* out, U16 len)
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{
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#ifndef WITH_NO_DMA
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static uint8_t buf[MAX_BLOCK_LEN];
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/* unaligned data or odd number of bytes, then skip dma */
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if ((U32) in % 4 || (U32) out % 4 || len % 2) {
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fifo_txrx(in, out, len);
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} else {
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if (in == NULL) {
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memset(buf, 0xff, len);
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in = buf;
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} else if (out == NULL) {
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out = buf;
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}
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dma_txrx(in, out, len);
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}
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#else
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fifo_txrx(in, out, len);
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#endif
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}
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void owl_spi_irq(U8 enable)
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{
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#ifdef WL_IRQ_PIN
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if (enable)
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gpio_enable_pin_interrupt(WL_IRQ_PIN, GPIO_PIN_CHANGE);
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else
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gpio_disable_pin_interrupt(WL_IRQ_PIN);
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#endif
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}
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void owl_spi_cs(U8 enable)
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{
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volatile avr32_spi_t *spi = &WL_SPI;
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/*
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* PCS = xxx0 => NPCS[3:0] = 1110
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* PCS = xx01 => NPCS[3:0] = 1101
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* PCS = x011 => NPCS[3:0] = 1011
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* PCS = 0111 => NPCS[3:0] = 0111
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* PCS = 1111 => forbidden (no peripheral is selected)
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*/
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if (enable)
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#if WL_SPI_CS == 2
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spi->MR.pcs = 0x3; /* cs2 */
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#elif WL_SPI_CS == 1
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spi->MR.pcs = 0x1; /* cs1 */
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#elif WL_SPI_CS == 3
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spi->MR.pcs = 0x7; /* cs3 */
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#elif WL_SPI_CS == 0
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spi->MR.pcs = 0x0; /* cs0 */
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#endif
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else
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spi->MR.pcs = 0xf;
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}
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void owl_spi_mdelay(uint32_t ms)
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{
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volatile int a = 0;
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int i;
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for (i = 0; i < ms * 5000; i++)
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a++;
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}
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__attribute__((__interrupt__)) void avr32_irq_handler(void)
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{
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#ifndef WITH_NO_DMA
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volatile avr32_pdca_channel_t *pdca_tx = &AVR32_PDCA.channel[0];
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volatile avr32_pdca_channel_t *pdca_rx = &AVR32_PDCA.channel[1];
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/* tx xfer complete */
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if (pdca_tx->IMR.trc && pdca_tx->ISR.trc) {
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pdca_tx->IDR.trc = 1;
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pdca_tx->CR.tdis = 1; /* disable tx xfer */
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}
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/* rx xfer complete */
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if (pdca_rx->IMR.trc && pdca_rx->ISR.trc) {
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pdca_rx->IDR.trc = 1;
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pdca_rx->CR.tdis = 1; /* disable rx xfer */
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}
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#endif
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#ifdef WL_IRQ_PIN
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if (gpio_get_pin_interrupt_flag(WL_IRQ_PIN)) {
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gpio_clear_pin_interrupt_flag(WL_IRQ_PIN);
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wl_spi_irq();
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}
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#endif
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}
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