Aaron Fischer
f24858d162
This step seems bold, but is saves us so much hassle. Even better, we have a reliable codebase, with all the dependencies (and their versions) we need in order to build the project. If a library got an update, we can replace it inplace if the code is still compatible.
547 lines
14 KiB
C
547 lines
14 KiB
C
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief Power Manager driver.
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*
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*
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* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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* - Supported devices: All AVR32 devices.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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*****************************************************************************/
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/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an Atmel
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* AVR product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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*
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*/
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#include "compiler.h"
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#include "pm.h"
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/*! \name PM Writable Bit-Field Registers
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*/
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//! @{
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typedef union
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{
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unsigned long mcctrl;
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avr32_pm_mcctrl_t MCCTRL;
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} u_avr32_pm_mcctrl_t;
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typedef union
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{
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unsigned long cksel;
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avr32_pm_cksel_t CKSEL;
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} u_avr32_pm_cksel_t;
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typedef union
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{
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unsigned long pll;
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avr32_pm_pll_t PLL;
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} u_avr32_pm_pll_t;
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typedef union
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{
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unsigned long oscctrl0;
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avr32_pm_oscctrl0_t OSCCTRL0;
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} u_avr32_pm_oscctrl0_t;
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typedef union
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{
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unsigned long oscctrl1;
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avr32_pm_oscctrl1_t OSCCTRL1;
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} u_avr32_pm_oscctrl1_t;
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typedef union
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{
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unsigned long oscctrl32;
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avr32_pm_oscctrl32_t OSCCTRL32;
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} u_avr32_pm_oscctrl32_t;
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typedef union
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{
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unsigned long ier;
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avr32_pm_ier_t IER;
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} u_avr32_pm_ier_t;
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typedef union
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{
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unsigned long idr;
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avr32_pm_idr_t IDR;
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} u_avr32_pm_idr_t;
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typedef union
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{
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unsigned long icr;
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avr32_pm_icr_t ICR;
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} u_avr32_pm_icr_t;
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typedef union
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{
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unsigned long gcctrl;
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avr32_pm_gcctrl_t GCCTRL;
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} u_avr32_pm_gcctrl_t;
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typedef union
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{
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unsigned long rccr;
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avr32_pm_rccr_t RCCR;
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} u_avr32_pm_rccr_t;
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typedef union
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{
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unsigned long bgcr;
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avr32_pm_bgcr_t BGCR;
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} u_avr32_pm_bgcr_t;
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typedef union
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{
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unsigned long vregcr;
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avr32_pm_vregcr_t VREGCR;
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} u_avr32_pm_vregcr_t;
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typedef union
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{
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unsigned long bod;
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avr32_pm_bod_t BOD;
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} u_avr32_pm_bod_t;
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//! @}
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/*! \brief Sets the mode of the oscillator 0.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
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* \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x).
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*/
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static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode)
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{
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// Read
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u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
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// Modify
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u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode;
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// Write
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pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
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}
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void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)
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{
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pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK);
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}
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void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)
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{
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pm_set_osc0_mode(pm, (fosc0 < 900000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0 :
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(fosc0 < 3000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1 :
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(fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :
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AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3);
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}
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void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)
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{
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pm_enable_clk0_no_wait(pm, startup);
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pm_wait_for_clk0_ready(pm);
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}
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void pm_disable_clk0(volatile avr32_pm_t *pm)
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{
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pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK;
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}
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void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
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{
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// Read register
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u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
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// Modify
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u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup;
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// Write back
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pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
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pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK;
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}
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void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)
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{
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while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK));
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}
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/*! \brief Sets the mode of the oscillator 1.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
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* \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x).
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*/
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static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode)
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{
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// Read
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u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
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// Modify
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u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode;
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// Write
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pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
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}
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void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)
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{
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pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK);
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}
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void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)
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{
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pm_set_osc1_mode(pm, (fosc1 < 900000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G0 :
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(fosc1 < 3000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G1 :
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(fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :
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AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3);
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}
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void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)
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{
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pm_enable_clk1_no_wait(pm, startup);
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pm_wait_for_clk1_ready(pm);
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}
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void pm_disable_clk1(volatile avr32_pm_t *pm)
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{
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pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK;
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}
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void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
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{
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// Read register
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u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
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// Modify
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u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup;
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// Write back
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pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
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pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK;
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}
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void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)
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{
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while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK));
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}
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/*! \brief Sets the mode of the 32-kHz oscillator.
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*
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* \param pm Base address of the Power Manager (i.e. &AVR32_PM).
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* \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x).
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*/
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static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode)
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{
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// Read
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u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
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// Modify
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u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode;
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// Write
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pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
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}
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void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)
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{
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pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK);
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}
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void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)
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{
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pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL);
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}
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void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)
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{
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pm_enable_clk32_no_wait(pm, startup);
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pm_wait_for_clk32_ready(pm);
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}
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void pm_disable_clk32(volatile avr32_pm_t *pm)
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{
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pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK;
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}
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void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
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{
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// Read register
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u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
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// Modify
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u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1;
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u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup;
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// Write back
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pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
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}
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void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)
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{
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while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK));
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}
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void pm_cksel(volatile avr32_pm_t *pm,
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unsigned int pbadiv,
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unsigned int pbasel,
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unsigned int pbbdiv,
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unsigned int pbbsel,
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unsigned int hsbdiv,
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unsigned int hsbsel)
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{
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u_avr32_pm_cksel_t u_avr32_pm_cksel = {0};
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u_avr32_pm_cksel.CKSEL.cpusel = hsbsel;
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u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv;
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u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel;
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u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv;
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u_avr32_pm_cksel.CKSEL.pbasel = pbasel;
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u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv;
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u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel;
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u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv;
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pm->cksel = u_avr32_pm_cksel.cksel;
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// Wait for ckrdy bit and then clear it
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while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));
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}
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void pm_gc_setup(volatile avr32_pm_t *pm,
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unsigned int gc,
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unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
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unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
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unsigned int diven,
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unsigned int div)
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{
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u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0};
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u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc;
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u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll;
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u_avr32_pm_gcctrl.GCCTRL.diven = diven;
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u_avr32_pm_gcctrl.GCCTRL.div = div;
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pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl;
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}
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void pm_gc_enable(volatile avr32_pm_t *pm,
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unsigned int gc)
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{
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pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK;
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}
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void pm_gc_disable(volatile avr32_pm_t *pm,
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unsigned int gc)
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{
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pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK;
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}
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void pm_pll_setup(volatile avr32_pm_t *pm,
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unsigned int pll,
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unsigned int mul,
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unsigned int div,
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unsigned int osc,
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unsigned int lockcount)
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{
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u_avr32_pm_pll_t u_avr32_pm_pll = {0};
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u_avr32_pm_pll.PLL.pllosc = osc;
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u_avr32_pm_pll.PLL.plldiv = div;
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u_avr32_pm_pll.PLL.pllmul = mul;
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u_avr32_pm_pll.PLL.pllcount = lockcount;
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pm->pll[pll] = u_avr32_pm_pll.pll;
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}
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void pm_pll_set_option(volatile avr32_pm_t *pm,
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unsigned int pll,
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unsigned int pll_freq,
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unsigned int pll_div2,
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unsigned int pll_wbwdisable)
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{
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u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]};
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u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2);
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pm->pll[pll] = u_avr32_pm_pll.pll;
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}
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unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,
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unsigned int pll)
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{
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return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET;
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}
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void pm_pll_enable(volatile avr32_pm_t *pm,
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unsigned int pll)
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{
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pm->pll[pll] |= AVR32_PM_PLLEN_MASK;
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}
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void pm_pll_disable(volatile avr32_pm_t *pm,
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unsigned int pll)
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{
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pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK;
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}
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void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)
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{
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while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK));
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}
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void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
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{
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while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK));
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}
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void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)
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{
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// Read
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u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};
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// Modify
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u_avr32_pm_mcctrl.MCCTRL.mcsel = clock;
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// Write back
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pm->mcctrl = u_avr32_pm_mcctrl.mcctrl;
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}
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void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)
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{
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pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode
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pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal
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pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0
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}
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void pm_bod_enable_irq(volatile avr32_pm_t *pm)
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{
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pm->ier = AVR32_PM_IER_BODDET_MASK;
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}
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void pm_bod_disable_irq(volatile avr32_pm_t *pm)
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{
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Bool global_interrupt_enabled = Is_global_interrupt_enabled();
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if (global_interrupt_enabled) Disable_global_interrupt();
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pm->idr = AVR32_PM_IDR_BODDET_MASK;
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pm->isr;
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if (global_interrupt_enabled) Enable_global_interrupt();
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}
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void pm_bod_clear_irq(volatile avr32_pm_t *pm)
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{
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pm->icr = AVR32_PM_ICR_BODDET_MASK;
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}
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unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm)
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{
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return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0);
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}
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unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm)
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{
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return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0);
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}
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unsigned long pm_bod_get_level(volatile avr32_pm_t *pm)
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{
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return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET;
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}
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unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp)
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{
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return pm->gplp[gplp];
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}
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void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value)
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{
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pm->gplp[gplp] = value;
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}
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long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module)
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{
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unsigned long domain = module>>5;
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unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain);
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// Implementation-specific shortcut: the ckMASK registers are contiguous and
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// memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
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*regptr |= (1<<(module%32));
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return PASS;
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}
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long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module)
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{
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unsigned long domain = module>>5;
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unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain);
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// Implementation-specific shortcut: the ckMASK registers are contiguous and
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// memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
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*regptr &= ~(1<<(module%32));
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return PASS;
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}
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