317 lines
11 KiB
C++
317 lines
11 KiB
C++
/*
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* si5351.h - Si5351 library for Arduino
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*
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* Copyright (C) 2015-2016 Jason Milldrum <milldrum@gmail.com>
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* Dana H. Myers <k6jq@comcast.net>
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*
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* Many defines derived from clk-si5351.h in the Linux kernel.
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Rabeeh Khoury <rabeeh@solid-run.com>
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*
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* do_div() macro derived from /include/asm-generic/div64.h in
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* the Linux kernel.
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* Copyright (C) 2003 Bernardo Innocenti <bernie@develer.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SI5351_H_
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#define SI5351_H_
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#include "Arduino.h"
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#include "Wire.h"
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#include <stdint.h>
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/* Define definitions */
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#define SI5351_BUS_BASE_ADDR 0x60
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#define SI5351_XTAL_FREQ 25000000
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#define SI5351_PLL_FIXED 90000000000ULL
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#define SI5351_FREQ_MULT 100ULL
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#define SI5351_DEFAULT_CLK 1000000000ULL
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#define SI5351_PLL_VCO_MIN 600000000
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#define SI5351_PLL_VCO_MAX 900000000
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#define SI5351_MULTISYNTH_MIN_FREQ 1000000
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#define SI5351_MULTISYNTH_DIVBY4_FREQ 150000000
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#define SI5351_MULTISYNTH_MAX_FREQ 160000000
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#define SI5351_MULTISYNTH_SHARE_MAX 112500000
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#define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ
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#define SI5351_CLKOUT_MIN_FREQ 8000
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#define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ
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#define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ
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#define SI5351_PLL_A_MIN 15
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#define SI5351_PLL_A_MAX 90
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#define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX-1)
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#define SI5351_PLL_C_MAX 1048575
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#define SI5351_MULTISYNTH_A_MIN 6
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#define SI5351_MULTISYNTH_A_MAX 1800
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#define SI5351_MULTISYNTH67_A_MAX 254
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#define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX-1)
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#define SI5351_MULTISYNTH_C_MAX 1048575
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#define SI5351_MULTISYNTH_P1_MAX ((1<<18)-1)
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#define SI5351_MULTISYNTH_P2_MAX ((1<<20)-1)
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#define SI5351_MULTISYNTH_P3_MAX ((1<<20)-1)
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#define SI5351_DEVICE_STATUS 0
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#define SI5351_INTERRUPT_STATUS 1
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#define SI5351_INTERRUPT_MASK 2
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#define SI5351_STATUS_SYS_INIT (1<<7)
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#define SI5351_STATUS_LOL_B (1<<6)
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#define SI5351_STATUS_LOL_A (1<<5)
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#define SI5351_STATUS_LOS (1<<4)
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#define SI5351_OUTPUT_ENABLE_CTRL 3
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#define SI5351_OEB_PIN_ENABLE_CTRL 9
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#define SI5351_PLL_INPUT_SOURCE 15
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#define SI5351_CLKIN_DIV_MASK (3<<6)
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#define SI5351_CLKIN_DIV_1 (0<<6)
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#define SI5351_CLKIN_DIV_2 (1<<6)
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#define SI5351_CLKIN_DIV_4 (2<<6)
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#define SI5351_CLKIN_DIV_8 (3<<6)
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#define SI5351_PLLB_SOURCE (1<<3)
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#define SI5351_PLLA_SOURCE (1<<2)
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#define SI5351_CLK0_CTRL 16
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#define SI5351_CLK1_CTRL 17
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#define SI5351_CLK2_CTRL 18
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#define SI5351_CLK3_CTRL 19
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#define SI5351_CLK4_CTRL 20
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#define SI5351_CLK5_CTRL 21
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#define SI5351_CLK6_CTRL 22
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#define SI5351_CLK7_CTRL 23
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#define SI5351_CLK_POWERDOWN (1<<7)
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#define SI5351_CLK_INTEGER_MODE (1<<6)
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#define SI5351_CLK_PLL_SELECT (1<<5)
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#define SI5351_CLK_INVERT (1<<4)
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#define SI5351_CLK_INPUT_MASK (3<<2)
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#define SI5351_CLK_INPUT_XTAL (0<<2)
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#define SI5351_CLK_INPUT_CLKIN (1<<2)
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#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2)
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#define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2)
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#define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0)
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#define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0)
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#define SI5351_CLK3_0_DISABLE_STATE 24
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#define SI5351_CLK7_4_DISABLE_STATE 25
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#define SI5351_CLK_DISABLE_STATE_MASK 3
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#define SI5351_CLK_DISABLE_STATE_LOW 0
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#define SI5351_CLK_DISABLE_STATE_HIGH 1
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#define SI5351_CLK_DISABLE_STATE_FLOAT 2
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#define SI5351_CLK_DISABLE_STATE_NEVER 3
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#define SI5351_PARAMETERS_LENGTH 8
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#define SI5351_PLLA_PARAMETERS 26
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#define SI5351_PLLB_PARAMETERS 34
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#define SI5351_CLK0_PARAMETERS 42
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#define SI5351_CLK1_PARAMETERS 50
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#define SI5351_CLK2_PARAMETERS 58
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#define SI5351_CLK3_PARAMETERS 66
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#define SI5351_CLK4_PARAMETERS 74
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#define SI5351_CLK5_PARAMETERS 82
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#define SI5351_CLK6_PARAMETERS 90
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#define SI5351_CLK7_PARAMETERS 91
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#define SI5351_CLK6_7_OUTPUT_DIVIDER 92
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#define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4)
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#define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0)
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#define SI5351_OUTPUT_CLK_DIV_SHIFT 4
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#define SI5351_OUTPUT_CLK_DIV6_SHIFT 0
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#define SI5351_OUTPUT_CLK_DIV_1 0
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#define SI5351_OUTPUT_CLK_DIV_2 1
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#define SI5351_OUTPUT_CLK_DIV_4 2
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#define SI5351_OUTPUT_CLK_DIV_8 3
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#define SI5351_OUTPUT_CLK_DIV_16 4
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#define SI5351_OUTPUT_CLK_DIV_32 5
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#define SI5351_OUTPUT_CLK_DIV_64 6
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#define SI5351_OUTPUT_CLK_DIV_128 7
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#define SI5351_OUTPUT_CLK_DIVBY4 (3<<2)
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#define SI5351_SSC_PARAM0 149
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#define SI5351_SSC_PARAM1 150
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#define SI5351_SSC_PARAM2 151
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#define SI5351_SSC_PARAM3 152
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#define SI5351_SSC_PARAM4 153
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#define SI5351_SSC_PARAM5 154
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#define SI5351_SSC_PARAM6 155
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#define SI5351_SSC_PARAM7 156
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#define SI5351_SSC_PARAM8 157
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#define SI5351_SSC_PARAM9 158
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#define SI5351_SSC_PARAM10 159
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#define SI5351_SSC_PARAM11 160
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#define SI5351_SSC_PARAM12 161
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#define SI5351_VXCO_PARAMETERS_LOW 162
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#define SI5351_VXCO_PARAMETERS_MID 163
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#define SI5351_VXCO_PARAMETERS_HIGH 164
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#define SI5351_CLK0_PHASE_OFFSET 165
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#define SI5351_CLK1_PHASE_OFFSET 166
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#define SI5351_CLK2_PHASE_OFFSET 167
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#define SI5351_CLK3_PHASE_OFFSET 168
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#define SI5351_CLK4_PHASE_OFFSET 169
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#define SI5351_CLK5_PHASE_OFFSET 170
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#define SI5351_PLL_RESET 177
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#define SI5351_PLL_RESET_B (1<<7)
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#define SI5351_PLL_RESET_A (1<<5)
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#define SI5351_CRYSTAL_LOAD 183
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#define SI5351_CRYSTAL_LOAD_MASK (3<<6)
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#define SI5351_CRYSTAL_LOAD_0PF (0<<6)
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#define SI5351_CRYSTAL_LOAD_6PF (1<<6)
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#define SI5351_CRYSTAL_LOAD_8PF (2<<6)
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#define SI5351_CRYSTAL_LOAD_10PF (3<<6)
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#define SI5351_FANOUT_ENABLE 187
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#define SI5351_CLKIN_ENABLE (1<<7)
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#define SI5351_XTAL_ENABLE (1<<6)
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#define SI5351_MULTISYNTH_ENABLE (1<<4)
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/* Macro definitions */
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#define RFRAC_DENOM ((1L << 20) - 1)
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/*
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* Based on former asm-ppc/div64.h and asm-m68knommu/div64.h
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*
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* The semantics of do_div() are:
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*
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* uint32_t do_div(uint64_t *n, uint32_t base)
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* {
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* uint32_t remainder = *n % base;
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* *n = *n / base;
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* return remainder;
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* }
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*
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* NOTE: macro parameter n is evaluated multiple times,
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* beware of side effects!
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*/
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# define do_div(n,base) ({ \
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uint64_t __base = (base); \
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uint64_t __rem; \
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__rem = ((uint64_t)(n)) % __base; \
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(n) = ((uint64_t)(n)) / __base; \
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__rem; \
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})
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/* Enum definitions */
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/*
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* enum si5351_variant - SiLabs Si5351 chip variant
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* @SI5351_VARIANT_A: Si5351A (8 output clocks, XTAL input)
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* @SI5351_VARIANT_A3: Si5351A MSOP10 (3 output clocks, XTAL input)
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* @SI5351_VARIANT_B: Si5351B (8 output clocks, XTAL/VXCO input)
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* @SI5351_VARIANT_C: Si5351C (8 output clocks, XTAL/CLKIN input)
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*/
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enum si5351_variant {SI5351_VARIANT_A, SI5351_VARIANT_A3, SI5351_VARIANT_B,
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SI5351_VARIANT_C};
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enum si5351_clock {SI5351_CLK0, SI5351_CLK1, SI5351_CLK2, SI5351_CLK3,
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SI5351_CLK4, SI5351_CLK5, SI5351_CLK6, SI5351_CLK7, SI5351_CLKNONE};
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enum si5351_pll {SI5351_PLLA, SI5351_PLLB};
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enum si5351_drive {SI5351_DRIVE_2MA, SI5351_DRIVE_4MA, SI5351_DRIVE_6MA,
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SI5351_DRIVE_8MA};
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enum si5351_clock_source {SI5351_CLK_SRC_XTAL, SI5351_CLK_SRC_CLKIN,
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SI5351_CLK_SRC_MS0, SI5351_CLK_SRC_MS};
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enum si5351_clock_disable {SI5351_CLK_DISABLE_LOW, SI5351_CLK_DISABLE_HIGH,
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SI5351_CLK_DISABLE_HI_Z, SI5351_CLK_DISABLE_NEVER};
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enum si5351_clock_fanout {SI5351_FANOUT_CLKIN, SI5351_FANOUT_XO,
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SI5351_FANOUT_MS};
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enum si5351_pll_input{SI5351_PLL_INPUT_XO, SI5351_PLL_INPUT_CLKIN};
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/* Struct definitions */
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struct Si5351RegSet
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{
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uint32_t p1;
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uint32_t p2;
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uint32_t p3;
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};
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struct Si5351Status
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{
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uint8_t SYS_INIT;
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uint8_t LOL_B;
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uint8_t LOL_A;
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uint8_t LOS;
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uint8_t REVID;
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};
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struct Si5351IntStatus
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{
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uint8_t SYS_INIT_STKY;
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uint8_t LOL_B_STKY;
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uint8_t LOL_A_STKY;
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uint8_t LOS_STKY;
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};
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class Si5351
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{
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public:
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Si5351(void);
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void init(uint8_t, uint32_t);
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uint8_t set_freq(uint64_t, uint64_t, enum si5351_clock);
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void set_pll(uint64_t, enum si5351_pll);
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void set_ms(enum si5351_clock, struct Si5351RegSet, uint8_t, uint8_t, uint8_t);
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void output_enable(enum si5351_clock, uint8_t);
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void drive_strength(enum si5351_clock, enum si5351_drive);
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void update_status(void);
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void set_correction(int32_t);
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void set_phase(enum si5351_clock, uint8_t);
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int32_t get_correction(void);
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void pll_reset(enum si5351_pll);
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void set_ms_source(enum si5351_clock, enum si5351_pll);
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void set_int(enum si5351_clock, uint8_t);
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void set_clock_pwr(enum si5351_clock, uint8_t);
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void set_clock_invert(enum si5351_clock, uint8_t);
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void set_clock_source(enum si5351_clock, enum si5351_clock_source);
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void set_clock_disable(enum si5351_clock, enum si5351_clock_disable);
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void set_clock_fanout(enum si5351_clock_fanout, uint8_t);
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void set_pll_input(enum si5351_pll, enum si5351_pll_input);
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uint8_t si5351_write_bulk(uint8_t, uint8_t, uint8_t *);
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uint8_t si5351_write(uint8_t, uint8_t);
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uint8_t si5351_read(uint8_t);
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struct Si5351Status dev_status;
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struct Si5351IntStatus dev_int_status;
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uint64_t plla_freq;
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uint64_t pllb_freq;
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uint64_t clk0_freq;
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uint64_t clk1_freq;
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uint64_t clk2_freq;
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uint8_t clk0_int_mode, clk1_int_mode, clk2_int_mode;
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private:
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uint64_t pll_calc(uint64_t, struct Si5351RegSet *, int32_t);
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uint64_t multisynth_calc(uint64_t, uint64_t, struct Si5351RegSet *);
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void update_sys_status(struct Si5351Status *);
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void update_int_status(struct Si5351IntStatus *);
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void ms_div(enum si5351_clock, uint8_t, uint8_t);
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uint8_t select_r_div(uint64_t *);
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int32_t ref_correction;
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uint8_t lock_plla, lock_pllb;
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uint32_t xtal_freq;
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};
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#endif /* SI5351_H_ */
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