Aaron Fischer
f24858d162
This step seems bold, but is saves us so much hassle. Even better, we have a reliable codebase, with all the dependencies (and their versions) we need in order to build the project. If a library got an update, we can replace it inplace if the code is still compatible.
567 lines
19 KiB
C
567 lines
19 KiB
C
/* This source file is part of the ATMEL AVR-UC3-SoftwareFramework-1.7.0 Release */
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/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief High-level library abstracting features such as oscillators/pll/dfll
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* configuration, clock configuration, System-sensible parameters
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* configuration, buses clocks configuration, sleep mode, reset.
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*
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*
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* - Compiler: IAR EWAVR32 and GNU GCC for AVR32
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* - Supported devices: All AVR32 devices.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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*****************************************************************************/
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/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an Atmel
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* AVR product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
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*
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*/
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#include "power_clocks_lib.h"
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//! Device-specific data
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#if UC3L
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static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param); // FORWARD declaration
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#endif
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#if UC3C
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static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param); // FORWARD declaration
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#endif
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long int pcl_configure_clocks(pcl_freq_param_t *param)
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{
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#ifndef AVR32_PM_VERSION_RESETVALUE
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// Implementation for UC3A, UC3A3, UC3B parts.
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return(pm_configure_clocks(param));
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#else
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#ifdef AVR32_PM_410_H_INCLUDED
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// Implementation for UC3C parts.
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return(pcl_configure_clocks_uc3c(param));
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#else
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// Implementation for UC3L parts.
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return(pcl_configure_clocks_uc3l(param));
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#endif
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#endif
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}
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//! Device-specific implementation
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#if UC3L
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// FORWARD declaration
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static long int pcl_configure_synchronous_clocks( pm_clk_src_t main_clk_src,
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unsigned long main_clock_freq_hz,
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pcl_freq_param_t *param);
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long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param)
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{
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// Supported main clock sources: PCL_MC_RCSYS
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// Supported synchronous clocks frequencies if RCSYS is the main clock source:
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// 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
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// NOTE: by default, this implementation doesn't perform thorough checks on the
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// input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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#ifdef AVR32SFW_INPUT_CHECK
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// Verify that fCPU >= fPBx
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if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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return(-1);
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#endif
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#ifdef AVR32SFW_INPUT_CHECK
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// Verify that the target frequencies are reachable.
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if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ)
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|| (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ))
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return(-1);
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#endif
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return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param));
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}
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long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param)
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{
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// Supported main clock sources: PCL_MC_RC120M
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// Supported synchronous clocks frequencies if RC120M is the main clock source:
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// 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
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// NOTE: by default, this implementation doesn't perform thorough checks on the
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// input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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#ifdef AVR32SFW_INPUT_CHECK
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// Verify that fCPU >= fPBx
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if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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return(-1);
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#endif
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#ifdef AVR32SFW_INPUT_CHECK
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// Verify that the target frequencies are reachable.
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if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)
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|| (param->pbb_f > SCIF_RC120M_FREQ_HZ))
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return(-1);
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#endif
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// Start the 120MHz internal RCosc (RC120M) clock
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scif_start_rc120M();
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return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));
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}
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long int pcl_configure_clocks_osc0(pcl_freq_param_t *param)
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{
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// Supported main clock sources: PCL_MC_OSC0
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// Supported synchronous clocks frequencies if OSC0 is the main clock source:
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// (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
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// 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
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// NOTE: by default, this implementation doesn't perform thorough checks on the
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// input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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unsigned long main_clock_freq;
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#ifdef AVR32SFW_INPUT_CHECK
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// Verify that fCPU >= fPBx
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if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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return(-1);
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#endif
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main_clock_freq = param->osc0_f;
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#ifdef AVR32SFW_INPUT_CHECK
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// Verify that the target frequencies are reachable.
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if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
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|| (param->pbb_f > main_clock_freq))
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return(-1);
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#endif
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// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
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scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);
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// Enable the OSC0
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scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
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return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));
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}
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long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param)
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{
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// Supported main clock sources: PCL_MC_DFLL
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// Supported synchronous clocks frequencies if DFLL is the main clock source:
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// (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
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// 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
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// NOTE: by default, this implementation doesn't perform thorough checks on the
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// input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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unsigned long main_clock_freq;
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scif_gclk_opt_t *pgc_dfllif_ref_opt;
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#ifdef AVR32SFW_INPUT_CHECK
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// Verify that fCPU >= fPBx
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if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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return(-1);
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#endif
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main_clock_freq = param->dfll_f;
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#ifdef AVR32SFW_INPUT_CHECK
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// Verify that the target DFLL output frequency is in the correct range.
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if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ))
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return(-1);
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// Verify that the target frequencies are reachable.
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if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
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|| (param->pbb_f > main_clock_freq))
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return(-1);
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#endif
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pgc_dfllif_ref_opt = (scif_gclk_opt_t *)param->pextra_params;
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// Implementation note: this implementation configures the DFLL in closed-loop
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// mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF
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// as a reference (RCSYS being used as the generic clock source, undivided).
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scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, TRUE);
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return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));
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}
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static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param)
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{
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// Supported main clock sources: PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_DFLL0, PCL_MC_RC120M
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// Supported synchronous clocks frequencies if RCSYS is the main clock source:
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// 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
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// Supported synchronous clocks frequencies if RC120M is the main clock source:
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// 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
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// Supported synchronous clocks frequencies if OSC0 is the main clock source:
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// (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
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// 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
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// Supported synchronous clocks frequencies if DFLL is the main clock source:
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// (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
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// 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
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// NOTE: by default, this implementation doesn't perform thorough checks on the
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// input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
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#ifdef AVR32SFW_INPUT_CHECK
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// Verify that fCPU >= fPBx
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if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
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return(-1);
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#endif
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if(PCL_MC_RCSYS == param->main_clk_src)
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{
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return(pcl_configure_clocks_rcsys(param));
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}
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else if(PCL_MC_RC120M == param->main_clk_src)
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{
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return(pcl_configure_clocks_rc120m(param));
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}
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else if(PCL_MC_OSC0 == param->main_clk_src)
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{
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return(pcl_configure_clocks_osc0(param));
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}
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else // PCL_MC_DFLL0 == param->main_clk_src
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{
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return(pcl_configure_clocks_dfll0(param));
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}
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}
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static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
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{
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//#
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//# Set the Synchronous clock division ratio for each clock domain
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//#
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pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);
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//#
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//# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
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//#
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#if UC3L
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flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
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#elif UC3C
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flashc_set_flash_waitstate_and_readmode(param->cpu_f);
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#endif
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//#
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//# Switch the main clock source to the selected clock.
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//#
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pm_set_mclk_source(main_clk_src);
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return PASS;
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}
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#endif // UC3L device-specific implementation
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//! UC3C Device-specific implementation
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#if UC3C
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static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
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{
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#define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
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#define AVR32_PM_PBA_MAX_FREQ 66000000
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#define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000
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#define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000
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// Implementation for UC3C parts.
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// Supported frequencies:
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// Fosc0 mul div PLL div2_en cpu_f pba_f Comment
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// 12 15 1 192 1 12 12
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// 12 9 3 40 1 20 20 PLL out of spec
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// 12 15 1 192 1 24 12
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// 12 9 1 120 1 30 15
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// 12 9 3 40 0 40 20 PLL out of spec
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// 12 15 1 192 1 48 12
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// 12 15 1 192 1 48 24
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// 12 8 1 108 1 54 27
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// 12 9 1 120 1 60 15
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// 12 9 1 120 1 60 30
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// 12 10 1 132 1 66 16.5
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//
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unsigned long in_cpu_f = param->cpu_f;
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unsigned long in_osc0_f = param->osc0_f;
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unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
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unsigned long pll_freq, rest;
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Bool b_div2_pba, b_div2_cpu;
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// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
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scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
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// Enable the OSC0
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scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
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// Set the main clock source as being OSC0.
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pm_set_mclk_source(PM_CLK_SRC_OSC0);
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// Start with CPU freq config
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if (in_cpu_f == in_osc0_f)
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{
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param->cpu_f = in_osc0_f;
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param->pba_f = in_osc0_f;
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return PASS;
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}
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else if (in_cpu_f < in_osc0_f)
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{
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// TBD
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}
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rest = in_cpu_f % in_osc0_f;
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for (div = 1; div < 32; div++)
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{
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if ((div * rest) % in_osc0_f == 0)
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break;
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}
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if (div == 32)
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return FAIL;
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mul = (in_cpu_f * div) / in_osc0_f;
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if (mul > PM_MAX_MUL)
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return FAIL;
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// export 2power from PLL div to div2_cpu
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while (!(div % 2))
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{
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div /= 2;
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div2_cpu++;
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}
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// Here we know the mul and div parameter of the PLL config.
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// . Check out if the PLL has a valid in_cpu_f.
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// . Try to have for the PLL frequency (VCO output) the highest possible value
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// to reduce jitter.
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while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
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{
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if (2 * mul > PM_MAX_MUL)
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break;
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mul *= 2;
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div2_cpu++;
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}
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if (div2_cpu != 0)
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{
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div2_cpu--;
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div2_en = 1;
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}
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pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
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// Update real CPU Frequency
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param->cpu_f = pll_freq / (1 << div2_cpu);
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mul--;
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scif_pll_opt_t opt;
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opt.osc = SCIF_OSC0, // Sel Osc0 or Osc1
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opt.lockcount = 16, // lockcount in main clock for the PLL wait lock
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opt.div = div, // DIV=1 in the formula
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opt.mul = mul, // MUL=7 in the formula
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opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
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opt.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
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opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
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scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
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/* Enable PLL0 */
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scif_pll_enable(SCIF_PLL0);
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/* Wait for PLL0 locked */
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scif_wait_for_pll_locked(SCIF_PLL0) ;
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rest = pll_freq;
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while (rest > AVR32_PM_PBA_MAX_FREQ ||
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rest != param->pba_f)
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{
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div2_pba++;
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rest = pll_freq / (1 << div2_pba);
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if (rest < param->pba_f)
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break;
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}
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// Update real PBA Frequency
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param->pba_f = pll_freq / (1 << div2_pba);
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if (div2_cpu)
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{
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b_div2_cpu = TRUE;
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div2_cpu--;
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}
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else
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b_div2_cpu = FALSE;
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if (div2_pba)
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{
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b_div2_pba = TRUE;
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div2_pba--;
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}
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else
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b_div2_pba = FALSE;
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if (b_div2_cpu == TRUE )
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{
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pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU
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pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB
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pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB
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}
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if (b_div2_pba == TRUE )
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{
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pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA
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pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC
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}
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|
|
|
// Set Flashc Wait State
|
|
flashc_set_flash_waitstate_and_readmode(param->cpu_f);
|
|
|
|
// Set the main clock source as being PLL0.
|
|
pm_set_mclk_source(PM_CLK_SRC_PLL0);
|
|
|
|
return PASS;
|
|
}
|
|
#endif // UC3C device-specific implementation
|
|
|
|
long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
|
|
{
|
|
#ifndef AVR32_PM_VERSION_RESETVALUE
|
|
// Implementation for UC3A, UC3A3, UC3B parts.
|
|
if(PCL_OSC0 == osc)
|
|
{
|
|
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,
|
|
// enable the OSC0, set the main clock source as being OSC0.
|
|
pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
|
|
}
|
|
else
|
|
{
|
|
return PCL_NOT_SUPPORTED;
|
|
}
|
|
#else
|
|
// Implementation for UC3C, UC3L parts.
|
|
#if AVR32_PM_VERSION_RESETVALUE < 0x400
|
|
return PCL_NOT_SUPPORTED;
|
|
#else
|
|
if(PCL_OSC0 == osc)
|
|
{
|
|
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
|
|
scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
|
|
// Enable the OSC0
|
|
scif_enable_osc(SCIF_OSC0, startup, true);
|
|
// Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
|
|
#if UC3L
|
|
flashcdw_set_flash_waitstate_and_readmode(fcrystal);
|
|
#elif UC3C
|
|
flashc_set_flash_waitstate_and_readmode(fcrystal);
|
|
#endif
|
|
// Set the main clock source as being OSC0.
|
|
pm_set_mclk_source(PM_CLK_SRC_OSC0);
|
|
}
|
|
else
|
|
{
|
|
return PCL_NOT_SUPPORTED;
|
|
}
|
|
#endif
|
|
#endif
|
|
return PASS;
|
|
}
|
|
|
|
long int pcl_configure_usb_clock(void)
|
|
{
|
|
#ifndef AVR32_PM_VERSION_RESETVALUE
|
|
// Implementation for UC3A, UC3A3, UC3B parts.
|
|
pm_configure_usb_clock();
|
|
return PASS;
|
|
#else
|
|
#ifdef AVR32_PM_410_H_INCLUDED
|
|
const scif_pll_opt_t opt = {
|
|
.osc = SCIF_OSC0, // Sel Osc0 or Osc1
|
|
.lockcount = 16, // lockcount in main clock for the PLL wait lock
|
|
.div = 1, // DIV=1 in the formula
|
|
.mul = 5, // MUL=7 in the formula
|
|
.pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
|
|
.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
|
|
.pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
|
|
};
|
|
|
|
/* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */
|
|
scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock
|
|
|
|
/* Enable PLL1 */
|
|
scif_pll_enable(SCIF_PLL1);
|
|
|
|
/* Wait for PLL1 locked */
|
|
scif_wait_for_pll_locked(SCIF_PLL1) ;
|
|
|
|
// Implementation for UC3C parts.
|
|
// Setup the generic clock for USB
|
|
scif_gc_setup(AVR32_SCIF_GCLK_USB,
|
|
SCIF_GCCTRL_PLL1,
|
|
AVR32_SCIF_GC_NO_DIV_CLOCK,
|
|
0);
|
|
// Now enable the generic clock
|
|
scif_gc_enable(AVR32_SCIF_GCLK_USB);
|
|
return PASS;
|
|
#else
|
|
return PCL_NOT_SUPPORTED;
|
|
#endif
|
|
#endif
|
|
}
|
|
|
|
|
|
#if UC3L
|
|
#else
|
|
void pcl_write_gplp(unsigned long gplp, unsigned long value)
|
|
{
|
|
#ifndef AVR32_PM_VERSION_RESETVALUE
|
|
// Implementation for UC3A, UC3A3, UC3B parts.
|
|
pm_write_gplp(&AVR32_PM,gplp,value);
|
|
#else
|
|
scif_write_gplp(gplp,value);
|
|
#endif
|
|
}
|
|
|
|
unsigned long pcl_read_gplp(unsigned long gplp)
|
|
{
|
|
#ifndef AVR32_PM_VERSION_RESETVALUE
|
|
// Implementation for UC3A, UC3A3, UC3B parts.
|
|
return pm_read_gplp(&AVR32_PM,gplp);
|
|
#else
|
|
return scif_read_gplp(gplp);
|
|
#endif
|
|
}
|
|
#endif
|