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weatherstation/schematics/oko-weatherstation.kicad_pcb

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adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(kicad_pcb (version 20171130) (host pcbnew 5.0.2-4.fc29)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(general
(thickness 1.6)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(drawings 45)
(tracks 175)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(zones 0)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(modules 32)
(nets 27)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
Change PCB to square
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(43 Eco2.User user hide)
Make a nice PCB to hold the components on the board
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(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user hide)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(user_trace_width 0.4)
(user_trace_width 0.5)
(user_trace_width 0.6)
Make a nice PCB to hold the components on the board
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(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
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(pad_size 1.5 1.5)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(pad_drill 0)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad_to_mask_clearance 0)
(solder_mask_min_width 0.25)
Change PCB to square
2019-01-30 09:30:51 +01:00
(aux_axis_origin 128 81.5)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
Change PCB to square
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(usegerberextensions true)
Make a nice PCB to hold the components on the board
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(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
Change PCB to square
2019-01-30 09:30:51 +01:00
(excludeedgelayer false)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
Change PCB to square
2019-01-30 09:30:51 +01:00
(useauxorigin true)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
Change PCB to square
2019-01-30 09:30:51 +01:00
(subtractmaskfromsilk true)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(outputformat 1)
(mirror false)
Change PCB to square
2019-01-30 09:30:51 +01:00
(drillshape 0)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 1 5V)
(net 2 GND)
(net 3 SCL)
(net 4 SDA)
(net 5 3V3)
(net 6 "Net-(U3-Pad6)")
(net 7 VCC_SOLAR)
(net 8 GND_SOLAR)
(net 9 ANEMOMETER)
(net 10 "Net-(JP1-Pad2)")
(net 11 "Net-(JP1-Pad1)")
(net 12 VCC_BAT)
(net 13 GND_BAT)
(net 14 "Net-(R1-Pad2)")
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 15 "Net-(U2-Pad7)")
(net 16 "Net-(U2-Pad8)")
(net 17 "Net-(U3-Pad1)")
(net 18 "Net-(U4-Pad1)")
(net 19 "Net-(U4-Pad2)")
(net 20 BAT_CHARGING)
(net 21 BAT_CHARGED)
(net 22 GPIO3)
(net 23 GPIO4)
(net 24 GPIO8)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(net 25 NCHRG)
(net 26 NSTBY)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net 3V3)
(add_net 5V)
(add_net ANEMOMETER)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(add_net BAT_CHARGED)
(add_net BAT_CHARGING)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(add_net GND)
(add_net GND_BAT)
(add_net GND_SOLAR)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(add_net GPIO3)
(add_net GPIO4)
(add_net GPIO8)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(add_net NCHRG)
(add_net NSTBY)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(add_net "Net-(JP1-Pad1)")
(add_net "Net-(JP1-Pad2)")
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(add_net "Net-(R1-Pad2)")
(add_net "Net-(U2-Pad7)")
(add_net "Net-(U2-Pad8)")
(add_net "Net-(U3-Pad1)")
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(add_net "Net-(U3-Pad6)")
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(add_net "Net-(U4-Pad1)")
(add_net "Net-(U4-Pad2)")
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(add_net SCL)
(add_net SDA)
(add_net VCC_BAT)
(add_net VCC_SOLAR)
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
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Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
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Change PCB to square
2019-01-30 09:30:51 +01:00
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changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
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Change PCB to square
2019-01-30 09:30:51 +01:00
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2019-01-27 12:29:51 +01:00
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Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user CSB (at 8.4 7.3 180) (layer F.SilkS) hide
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user SDA (at 8.3 5.9 180) (layer F.SilkS) hide
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user SCL (at 8.2 4.6 180) (layer F.SilkS) hide
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user GND (at 8.1 3.2 180) (layer F.SilkS) hide
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user VCC (at 8.5 8.6 180) (layer F.SilkS) hide
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user BME280 (at 11.1 6.1 270) (layer F.SilkS) hide
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 13.4 1.4) (end 13.4 16.4) (layer F.SilkS) (width 0.15))
(fp_line (start 1.4 16.4) (end 13.4 16.4) (layer F.SilkS) (width 0.15))
(fp_line (start 1.4 1.4) (end 13.4 1.4) (layer F.SilkS) (width 0.15))
(fp_line (start 1.4 1.4) (end 1.4 16.4) (layer F.SilkS) (width 0.15))
(pad 6 thru_hole circle (at 2.54 2.54 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 5 3V3))
(pad 5 thru_hole circle (at 2.54 5.08 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 GND))
(pad 4 thru_hole circle (at 2.54 7.62 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 3 SCL))
(pad 3 thru_hole circle (at 2.54 10.16 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 4 SDA))
(pad 2 thru_hole circle (at 2.54 12.7 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 19 "Net-(U4-Pad2)"))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(pad 1 thru_hole circle (at 2.54 15.24 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 18 "Net-(U4-Pad1)"))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(module oko:GY-BME280 (layer F.Cu) (tedit 5C50A5BD) (tstamp 5C37DABA)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(at 132.5 98.5 180)
(path /5C36680F)
(fp_text reference U4 (at 3.2 17.4 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value GY-BME280 (at 9.2 0.4 180) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user SDO (at -0.4 9.6 180) (layer F.SilkS)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user CSB (at -0.3 8.2 180) (layer F.SilkS)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user SDA (at -0.3 6.8 180) (layer F.SilkS)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user SCL (at -0.3 5.4 180) (layer F.SilkS)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user GND (at -0.4 3.9 180) (layer F.SilkS)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user VCC (at -0.4 2.3 180) (layer F.SilkS)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user BME280 (at 3.8 4.5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 13.4 1.4) (end 13.4 16.4) (layer F.SilkS) (width 0.15))
(fp_line (start 1.4 16.4) (end 13.4 16.4) (layer F.SilkS) (width 0.15))
(fp_line (start 1.4 1.4) (end 13.4 1.4) (layer F.SilkS) (width 0.15))
(fp_line (start 1.4 1.4) (end 1.4 16.4) (layer F.SilkS) (width 0.15))
(pad 6 thru_hole circle (at 2.54 2.54 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 5 3V3))
(pad 5 thru_hole circle (at 2.54 5.08 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 GND))
(pad 4 thru_hole circle (at 2.54 7.62 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 3 SCL))
(pad 3 thru_hole circle (at 2.54 10.16 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 4 SDA))
(pad 2 thru_hole circle (at 2.54 12.7 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 19 "Net-(U4-Pad2)"))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(pad 1 thru_hole circle (at 2.54 15.24 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 18 "Net-(U4-Pad1)"))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(module oko:APDS-9960 (layer F.Cu) (tedit 5C390407) (tstamp 5C37DAA5)
(at 140.5 114.5 180)
(path /5C366782)
(fp_text reference U3 (at 12.7 15.24 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value APDS-9900 (at 7.62 17.78 180) (layer F.Fab) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.3 1.44) (end 1.3 16.44) (layer F.SilkS) (width 0.15))
(fp_line (start 1.3 1.44) (end 21.3 1.44) (layer F.SilkS) (width 0.15))
(fp_line (start 21.3 1.44) (end 21.3 16.44) (layer F.SilkS) (width 0.15))
(fp_line (start 21.3 16.44) (end 1.3 16.44) (layer F.SilkS) (width 0.15))
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(fp_text user "VL " (at -0.2 15.44 180) (layer F.SilkS)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(fp_text user GND (at -0.3 16.71 180) (layer F.SilkS)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(fp_text user VCC (at -0.4 17.98 180) (layer F.SilkS)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(fp_text user SDA (at -0.3 19.25 180) (layer F.SilkS)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(fp_text user SCL (at -0.3 20.52 180) (layer F.SilkS)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(fp_text user INT (at -0.1 21.79 180) (layer F.SilkS)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user ADPS-9960 (at 4.5 6.4 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole circle (at 2.54 2.54 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 17 "Net-(U3-Pad1)"))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(pad 2 thru_hole circle (at 2.54 5.08 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 2 GND))
(pad 3 thru_hole circle (at 2.54 7.62 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 5 3V3))
(pad 4 thru_hole circle (at 2.54 10.16 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 4 SDA))
(pad 5 thru_hole circle (at 2.54 12.7 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 3 SCL))
(pad 6 thru_hole circle (at 2.54 15.24 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
(net 6 "Net-(U3-Pad6)"))
)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(module Pin_Headers:Pin_Header_Angled_1x02_Pitch2.54mm (layer B.Cu) (tedit 59650532) (tstamp 5C37DA77)
Change PCB to square
2019-01-30 09:30:51 +01:00
(at 173.9 86.5)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(descr "Through hole angled pin header, 1x02, 2.54mm pitch, 6mm pin length, single row")
(tags "Through hole angled pin header THT 1x02 2.54mm single row")
(path /5C3808D5)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text reference JP1 (at 4.385 2.27) (layer B.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text value Jumper (at 4.385 -4.81) (layer B.Fab)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 2.135 1.27) (end 4.04 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 1.27) (end 4.04 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -3.81) (end 1.5 -3.81) (layer B.Fab) (width 0.1))
(fp_line (start 1.5 -3.81) (end 1.5 0.635) (layer B.Fab) (width 0.1))
(fp_line (start 1.5 0.635) (end 2.135 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end 1.5 0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end -0.32 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -0.32) (end 1.5 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 0.32) (end 10.04 0.32) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 0.32) (end 10.04 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -0.32) (end 10.04 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.22) (end 1.5 -2.22) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.22) (end -0.32 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.86) (end 1.5 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -2.22) (end 10.04 -2.22) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 -2.22) (end 10.04 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -2.86) (end 10.04 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start 1.44 1.33) (end 1.44 -3.87) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -3.87) (end 4.1 -3.87) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -3.87) (end 4.1 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 1.33) (end 1.44 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.38) (end 10.1 0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 0.38) (end 10.1 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -0.38) (end 4.1 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.32) (end 10.1 0.32) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.2) (end 10.1 0.2) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.08) (end 10.1 0.08) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.04) (end 10.1 -0.04) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.16) (end 10.1 -0.16) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.28) (end 10.1 -0.28) (layer B.SilkS) (width 0.12))
(fp_line (start 1.11 0.38) (end 1.44 0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 1.11 -0.38) (end 1.44 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -1.27) (end 4.1 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -2.16) (end 10.1 -2.16) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -2.16) (end 10.1 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -2.92) (end 4.1 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -2.16) (end 1.44 -2.16) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -2.92) (end 1.44 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start -1.27 0) (end -1.27 1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.27 1.27) (end 0 1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 1.8) (end -1.8 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -4.35) (end 10.55 -4.35) (layer B.CrtYd) (width 0.05))
(fp_line (start 10.55 -4.35) (end 10.55 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 10.55 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text user %R (at 2.77 -1.27 -90) (layer B.Fab)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 11 "Net-(JP1-Pad1)"))
Change PCB to square
2019-01-30 09:30:51 +01:00
(pad 2 thru_hole oval (at 0 -2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 10 "Net-(JP1-Pad2)"))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Angled_1x02_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(module Capacitors_ThroughHole:C_Rect_L4.6mm_W2.0mm_P2.50mm_MKS02_FKP02 (layer B.Cu) (tedit 5C570890) (tstamp 5C37BB2B)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(at 146.6 103.1)
(descr "C, Rect series, Radial, pin pitch=2.50mm, , length*width=4.6*2mm^2, Capacitor, http://www.wima.de/DE/WIMA_MKS_02.pdf")
(tags "C Rect series Radial pin pitch 2.50mm length 4.6mm width 2mm Capacitor")
(path /5C36B0BF)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(fp_text reference C1 (at -2.3 0) (layer B.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(fp_text value 100n (at 1.25 -2.31) (layer B.Fab) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user %R (at 1.25 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 3.9 1.35) (end -1.4 1.35) (layer B.CrtYd) (width 0.05))
(fp_line (start 3.9 -1.35) (end 3.9 1.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.4 -1.35) (end 3.9 -1.35) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.4 1.35) (end -1.4 -1.35) (layer B.CrtYd) (width 0.05))
(fp_line (start 3.61 1.06) (end 3.61 -1.06) (layer B.SilkS) (width 0.12))
(fp_line (start -1.11 1.06) (end -1.11 -1.06) (layer B.SilkS) (width 0.12))
(fp_line (start -1.11 -1.06) (end 3.61 -1.06) (layer B.SilkS) (width 0.12))
(fp_line (start -1.11 1.06) (end 3.61 1.06) (layer B.SilkS) (width 0.12))
(fp_line (start 3.55 1) (end -1.05 1) (layer B.Fab) (width 0.1))
(fp_line (start 3.55 -1) (end 3.55 1) (layer B.Fab) (width 0.1))
(fp_line (start -1.05 -1) (end 3.55 -1) (layer B.Fab) (width 0.1))
(fp_line (start -1.05 1) (end -1.05 -1) (layer B.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.5 0) (size 1.4 1.4) (drill 0.7) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 9 ANEMOMETER))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 1 thru_hole circle (at 0 0) (size 1.4 1.4) (drill 0.7) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 2 GND))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(model ${KISYS3DMOD}/Capacitors_THT.3dshapes/C_Rect_L4.6mm_W2.0mm_P2.50mm_MKS02_FKP02.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(module Pin_Headers:Pin_Header_Angled_1x06_Pitch2.54mm (layer B.Cu) (tedit 5C51593B) (tstamp 5C37DA44)
(at 147.3 85.6 90)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(descr "Through hole angled pin header, 1x06, 2.54mm pitch, 6mm pin length, single row")
(tags "Through hole angled pin header THT 1x06 2.54mm single row")
(path /5C389FC7)
Change PCB to square
2019-01-30 09:30:51 +01:00
(fp_text reference J7 (at 4.385 2.27 90) (layer B.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_01x06 (at 4.385 -14.97 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user %R (at 2.77 -6.35) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 10.55 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 10.55 -14.5) (end 10.55 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -14.5) (end 10.55 -14.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end -1.8 -14.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.27 1.27) (end 0 1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.27 0) (end -1.27 1.27) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -13.08) (end 1.44 -13.08) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -12.32) (end 1.44 -12.32) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -13.08) (end 4.1 -13.08) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -12.32) (end 10.1 -13.08) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -12.32) (end 10.1 -12.32) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -11.43) (end 4.1 -11.43) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -10.54) (end 1.44 -10.54) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -9.78) (end 1.44 -9.78) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -10.54) (end 4.1 -10.54) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -9.78) (end 10.1 -10.54) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -9.78) (end 10.1 -9.78) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -8.89) (end 4.1 -8.89) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -8) (end 1.44 -8) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -7.24) (end 1.44 -7.24) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -8) (end 4.1 -8) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -7.24) (end 10.1 -8) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -7.24) (end 10.1 -7.24) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -6.35) (end 4.1 -6.35) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -5.46) (end 1.44 -5.46) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -4.7) (end 1.44 -4.7) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -5.46) (end 4.1 -5.46) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -4.7) (end 10.1 -5.46) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -4.7) (end 10.1 -4.7) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -3.81) (end 4.1 -3.81) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -2.92) (end 1.44 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 1.042929 -2.16) (end 1.44 -2.16) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -2.92) (end 4.1 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -2.16) (end 10.1 -2.92) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -2.16) (end 10.1 -2.16) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -1.27) (end 4.1 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start 1.11 -0.38) (end 1.44 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 1.11 0.38) (end 1.44 0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.28) (end 10.1 -0.28) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.16) (end 10.1 -0.16) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -0.04) (end 10.1 -0.04) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.08) (end 10.1 0.08) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.2) (end 10.1 0.2) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.32) (end 10.1 0.32) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 -0.38) (end 4.1 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 10.1 0.38) (end 10.1 -0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 0.38) (end 10.1 0.38) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 1.33) (end 1.44 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 4.1 -14.03) (end 4.1 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 -14.03) (end 4.1 -14.03) (layer B.SilkS) (width 0.12))
(fp_line (start 1.44 1.33) (end 1.44 -14.03) (layer B.SilkS) (width 0.12))
(fp_line (start 4.04 -13.02) (end 10.04 -13.02) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 -12.38) (end 10.04 -13.02) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -12.38) (end 10.04 -12.38) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -13.02) (end 1.5 -13.02) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -12.38) (end -0.32 -13.02) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -12.38) (end 1.5 -12.38) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -10.48) (end 10.04 -10.48) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 -9.84) (end 10.04 -10.48) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -9.84) (end 10.04 -9.84) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -10.48) (end 1.5 -10.48) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -9.84) (end -0.32 -10.48) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -9.84) (end 1.5 -9.84) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -7.94) (end 10.04 -7.94) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 -7.3) (end 10.04 -7.94) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -7.3) (end 10.04 -7.3) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -7.94) (end 1.5 -7.94) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -7.3) (end -0.32 -7.94) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -7.3) (end 1.5 -7.3) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -5.4) (end 10.04 -5.4) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 -4.76) (end 10.04 -5.4) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -4.76) (end 10.04 -4.76) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -5.4) (end 1.5 -5.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -4.76) (end -0.32 -5.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -4.76) (end 1.5 -4.76) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -2.86) (end 10.04 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 -2.22) (end 10.04 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -2.22) (end 10.04 -2.22) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.86) (end 1.5 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.22) (end -0.32 -2.86) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -2.22) (end 1.5 -2.22) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -0.32) (end 10.04 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start 10.04 0.32) (end 10.04 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 0.32) (end 10.04 0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 -0.32) (end 1.5 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end -0.32 -0.32) (layer B.Fab) (width 0.1))
(fp_line (start -0.32 0.32) (end 1.5 0.32) (layer B.Fab) (width 0.1))
(fp_line (start 1.5 0.635) (end 2.135 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.5 -13.97) (end 1.5 0.635) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 -13.97) (end 1.5 -13.97) (layer B.Fab) (width 0.1))
(fp_line (start 4.04 1.27) (end 4.04 -13.97) (layer B.Fab) (width 0.1))
(fp_line (start 2.135 1.27) (end 4.04 1.27) (layer B.Fab) (width 0.1))
(pad 6 thru_hole oval (at 0 -12.7 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 7 VCC_SOLAR))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 5 thru_hole oval (at 0 -10.16 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 8 GND_SOLAR))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 4 thru_hole oval (at 0 -7.62 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 12 VCC_BAT))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 3 thru_hole oval (at 0 -5.08 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 13 GND_BAT))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 2 thru_hole oval (at 0 -2.54 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 9 ANEMOMETER))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 2 GND))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Angled_1x06_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module oko:03962A (layer B.Cu) (tedit 5C39021A) (tstamp 5C37DA90)
(at 177.75 92.75 180)
(path /5C3666E0)
(fp_text reference U1 (at 2.3 0.8 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 03962A (at 5.75 -1.05 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 27.056963 -17.011121) (end 0.056963 -17.011121) (layer B.SilkS) (width 0.15))
(fp_line (start 0.056963 -0.011121) (end 27.056963 -0.011121) (layer B.SilkS) (width 0.15))
(fp_line (start 27.056963 -0.011121) (end 27.056963 -2.011121) (layer B.SilkS) (width 0.15))
(fp_line (start 27.056963 -2.011121) (end 26.056963 -3.011121) (layer B.SilkS) (width 0.15))
(fp_line (start 26.056963 -3.011121) (end 26.056963 -14.011121) (layer B.SilkS) (width 0.15))
(fp_line (start 26.056963 -14.011121) (end 27.056963 -15.011121) (layer B.SilkS) (width 0.15))
(fp_line (start 27.056963 -15.011121) (end 27.056963 -17.011121) (layer B.SilkS) (width 0.15))
(fp_line (start -1.1 -6) (end -1.1 -12) (layer B.SilkS) (width 0.15))
(fp_line (start -1.1 -12) (end 3.9 -12) (layer B.SilkS) (width 0.15))
(fp_line (start 3.9 -12) (end 3.9 -5) (layer B.SilkS) (width 0.15))
(fp_line (start 3.9 -5) (end -1.1 -5) (layer B.SilkS) (width 0.15))
(fp_line (start -1.1 -5) (end -1.1 -6) (layer B.SilkS) (width 0.15))
(fp_line (start 0 0) (end 0 -5) (layer B.SilkS) (width 0.15))
(fp_line (start 0 -12) (end 0 -17) (layer B.SilkS) (width 0.15))
(fp_text user 03962A (at 26.75 -6.85 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole rect (at 1.4 -1.4 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 7 VCC_SOLAR))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 2 thru_hole rect (at 24.9 -1.4 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 1 5V))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 3 thru_hole rect (at 24.9 -3.8 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 12 VCC_BAT))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 4 thru_hole rect (at 24.9 -13.2 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 13 GND_BAT))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 5 thru_hole rect (at 24.9 -15.6 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 2 GND))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 6 thru_hole rect (at 1.4 -15.6 180) (size 1.524 1.524) (drill 0.762) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 8 GND_SOLAR))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
)
(module oko:wemos-d1-mini-connectors-only (layer F.Cu) (tedit 5C3934BE) (tstamp 5C38D9A2)
(at 159.4 100 180)
(path /5C36643E)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(fp_text reference U2 (at -19.3 0 270) (layer F.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "WeMos D1 mini" (at 15.9 -5.1 90) (layer F.SilkS)
(effects (font (size 0.7 0.7) (thickness 0.15)))
)
(fp_line (start -18.3 13.33) (end 14.78 13.33) (layer F.SilkS) (width 0.15))
(fp_line (start 16.78 11.33) (end 16.78 -11.33) (layer F.SilkS) (width 0.15))
(fp_line (start 14.78 -13.33) (end -11.3 -13.33) (layer F.SilkS) (width 0.15))
(fp_line (start -18.3 -11.18) (end -18.3 -3.32) (layer F.SilkS) (width 0.15))
(fp_line (start -18.3 -3.32) (end -17.3 -3.32) (layer F.SilkS) (width 0.15))
(fp_line (start -17.3 -3.32) (end -17.3 4.9) (layer F.SilkS) (width 0.15))
(fp_line (start -17.3 4.9) (end -18.3 4.9) (layer F.SilkS) (width 0.15))
(fp_line (start -18.3 4.9) (end -18.3 13.329999) (layer F.SilkS) (width 0.15))
(fp_line (start -11.48 -13.5) (end 14.85 -13.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 16.94 -11.5) (end 16.94 11.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 14.94 13.5) (end -18.46 13.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -18.46 13.5) (end -18.46 -11.33) (layer F.CrtYd) (width 0.05))
(fp_arc (start 14.78 -11.33) (end 14.78 -13.33) (angle 90) (layer F.SilkS) (width 0.15))
(fp_arc (start 14.78 11.33) (end 16.78 11.33) (angle 90) (layer F.SilkS) (width 0.15))
(fp_arc (start 14.94 11.5) (end 16.94 11.5) (angle 90) (layer F.CrtYd) (width 0.05))
(fp_arc (start 14.94 -11.5) (end 14.85 -13.5) (angle 92.57657183) (layer F.CrtYd) (width 0.05))
(fp_line (start -18.3 -11.18) (end -12.3 -11.18) (layer F.SilkS) (width 0.15))
(fp_arc (start -12.3 -12.18) (end -11.3 -12.18) (angle 90) (layer F.SilkS) (width 0.15))
(fp_line (start -11.3 -12.17) (end -11.3 -13.33) (layer F.SilkS) (width 0.15))
(fp_line (start -11.3 -13.33) (end -11.3 -13.33) (layer F.SilkS) (width 0.15))
(fp_line (start -11.48 -13.5) (end -11.48 -12.33) (layer F.CrtYd) (width 0.05))
(fp_line (start -18.46 -11.33) (end -12.48 -11.33) (layer F.CrtYd) (width 0.05))
(fp_arc (start -12.48 -12.33) (end -11.48 -12.33) (angle 90) (layer F.CrtYd) (width 0.05))
(pad 16 thru_hole circle (at -8.89 -11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 5 3V3))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 1 thru_hole circle (at -8.89 11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 1 5V))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 15 thru_hole circle (at -6.35 -11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 24 GPIO8))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 2 thru_hole circle (at -6.35 11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 2 GND))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 14 thru_hole circle (at -3.81 -11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 9 ANEMOMETER))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 3 thru_hole circle (at -3.81 11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 23 GPIO4))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 13 thru_hole circle (at -1.27 -11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 21 BAT_CHARGED))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 4 thru_hole circle (at -1.27 11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 22 GPIO3))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 12 thru_hole circle (at 1.27 -11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 20 BAT_CHARGING))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 5 thru_hole circle (at 1.27 11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 4 SDA))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 11 thru_hole circle (at 3.81 -11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 11 "Net-(JP1-Pad1)"))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 6 thru_hole circle (at 3.81 11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 3 SCL))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 10 thru_hole circle (at 6.35 -11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 14 "Net-(R1-Pad2)"))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 7 thru_hole circle (at 6.35 11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 15 "Net-(U2-Pad7)"))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 9 thru_hole circle (at 8.89 -11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 10 "Net-(JP1-Pad2)"))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(pad 8 thru_hole circle (at 8.89 11.43 180) (size 1.8 1.8) (drill 1.016) (layers *.Cu *.Mask)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(net 16 "Net-(U2-Pad8)"))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(model ${KIPRJMOD}/3dshapes/wemos_d1_mini.3dshapes/SLW-108-01-G-S.wrl
(offset (xyz 0 -11.39999982878918 0))
(scale (xyz 0.3937 0.3937 0.3937))
(rotate (xyz -90 0 0))
)
(model ${KIPRJMOD}/3dshapes/wemos_d1_mini.3dshapes/SLW-108-01-G-S.wrl
(offset (xyz 0 11.39999982878918 0))
(scale (xyz 0.3937 0.3937 0.3937))
(rotate (xyz -90 0 0))
)
(model ${KIPRJMOD}/3dshapes/wemos_d1_mini.3dshapes/TSW-108-05-G-S.wrl
(offset (xyz 0 -11.39999982878918 7.299999890364999))
(scale (xyz 0.3937 0.3937 0.3937))
(rotate (xyz 90 0 0))
)
(model ${KIPRJMOD}/3dshapes/wemos_d1_mini.3dshapes/TSW-108-05-G-S.wrl
(offset (xyz 0 11.39999982878918 7.299999890364999))
(scale (xyz 0.3937 0.3937 0.3937))
(rotate (xyz 90 0 0))
)
)
(module Measurement_Points:Measurement_Point_Square-SMD-Pad_Small (layer B.Cu) (tedit 5C39021E) (tstamp 5C38D889)
(at 176.4 91)
(descr "Mesurement Point, Square, SMD Pad, 1.5mm x 1.5mm,")
(tags "Mesurement Point Square SMD Pad 1.5x1.5mm")
(path /5C38D2CB)
(attr virtual)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(fp_text reference J1 (at 0 2) (layer B.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value VCC_SOLAR (at 0 -2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1 -1) (end -1 1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 -1) (end -1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 1) (end 1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -1 1) (end 1 1) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at 0 0) (size 1.5 1.5) (layers B.Cu B.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 7 VCC_SOLAR))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
)
(module Measurement_Points:Measurement_Point_Square-SMD-Pad_Small (layer B.Cu) (tedit 5C3901F5) (tstamp 5C38D892)
(at 176.4 111.7)
(descr "Mesurement Point, Square, SMD Pad, 1.5mm x 1.5mm,")
(tags "Mesurement Point Square SMD Pad 1.5x1.5mm")
(path /5C38D8BF)
(attr virtual)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(fp_text reference J2 (at 0 2) (layer B.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value GND_SOLAR (at 7.5 -1.4) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1 1) (end 1 1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 1) (end 1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 -1) (end -1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -1 -1) (end -1 1) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at 0 0) (size 1.5 1.5) (layers B.Cu B.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 8 GND_SOLAR))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(module Measurement_Points:Measurement_Point_Square-SMD-Pad_Small (layer B.Cu) (tedit 5C3A6CE4) (tstamp 5C38D89B)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(at 149.5 96.5)
(descr "Mesurement Point, Square, SMD Pad, 1.5mm x 1.5mm,")
(tags "Mesurement Point Square SMD Pad 1.5x1.5mm")
(path /5C38D924)
(attr virtual)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(fp_text reference J3 (at -2.2 0) (layer B.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value VCC_BAT (at 0 -2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1 -1) (end -1 1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 -1) (end -1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 1) (end 1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -1 1) (end 1 1) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at 0 0) (size 1.5 1.5) (layers B.Cu B.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 12 VCC_BAT))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(module Measurement_Points:Measurement_Point_Square-SMD-Pad_Small (layer B.Cu) (tedit 5C3A6CFC) (tstamp 5C38D8A4)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(at 149.5 106)
(descr "Mesurement Point, Square, SMD Pad, 1.5mm x 1.5mm,")
(tags "Mesurement Point Square SMD Pad 1.5x1.5mm")
(path /5C38D96A)
(attr virtual)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(fp_text reference J4 (at -2.4 0) (layer B.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value GND_BAT (at 0 -2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1 1) (end 1 1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 1) (end 1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 -1) (end -1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -1 -1) (end -1 1) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at 0 0) (size 1.5 1.5) (layers B.Cu B.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 13 GND_BAT))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(module Measurement_Points:Measurement_Point_Square-SMD-Pad_Small (layer B.Cu) (tedit 5C3A6CE1) (tstamp 5C38D8AD)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(at 149 94.1)
(descr "Mesurement Point, Square, SMD Pad, 1.5mm x 1.5mm,")
(tags "Mesurement Point Square SMD Pad 1.5x1.5mm")
(path /5C38D9A1)
(attr virtual)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(fp_text reference J5 (at -3 1) (layer B.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 5V (at 0 -2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1 -1) (end -1 1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 -1) (end -1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 1) (end 1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -1 1) (end 1 1) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at 0 0) (size 1.5 1.5) (layers B.Cu B.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 1 5V))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(module Measurement_Points:Measurement_Point_Square-SMD-Pad_Small (layer B.Cu) (tedit 5C3A6D03) (tstamp 5C38D8B6)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(at 149 108.4)
(descr "Mesurement Point, Square, SMD Pad, 1.5mm x 1.5mm,")
(tags "Mesurement Point Square SMD Pad 1.5x1.5mm")
(path /5C38DB5F)
(attr virtual)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(fp_text reference J6 (at -3.1 0.1) (layer B.SilkS) hide
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value GND (at 0 -2) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1 1) (end 1 1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 1) (end 1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start 1 -1) (end -1 -1) (layer B.CrtYd) (width 0.05))
(fp_line (start -1 -1) (end -1 1) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at 0 0) (size 1.5 1.5) (layers B.Cu B.Mask)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(net 2 GND))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(module Resistors_SMD:R_0603_1608Metric (layer B.Cu) (tedit 5C4D95C9) (tstamp 5C4D9413)
minor changes
2019-01-27 13:11:12 +01:00
(at 137.782986 93.98 180)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5C4D91C5)
(attr smd)
(fp_text reference R2 (at 0 1.43 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 4k7 (at 0 -1.43 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -1.48 -0.73) (end -1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end 1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end 1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end -1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer B.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)) (justify mirror))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 5 3V3))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 4 SDA))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_1608Metric (layer B.Cu) (tedit 5C4D95D0) (tstamp 5C4D9424)
Change PCB to square
2019-01-30 09:30:51 +01:00
(at 137.782986 95.6 180)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5C4D924A)
(attr smd)
(fp_text reference R3 (at 0 1.43 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 4k7 (at 0 -1.43 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user %R (at 0 0 180) (layer B.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)) (justify mirror))
)
(fp_line (start 1.48 -0.73) (end -1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end 1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end 1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end -1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer B.SilkS) (width 0.12))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 3 SCL))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 5 3V3))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(module Mounting_Holes:MountingHole_2.5mm (layer F.Cu) (tedit 5C50A657) (tstamp 5C508E51)
(at 154.7 84.3)
(descr "Mounting Hole 2.5mm, no annular")
(tags "mounting hole 2.5mm no annular")
(attr virtual)
(fp_text reference REF** (at 0 -3.5) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MountingHole_2.5mm (at 0 3.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0.3 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2.5 0) (layer Cmts.User) (width 0.15))
(fp_circle (center 0 0) (end 2.75 0) (layer F.CrtYd) (width 0.05))
(pad 1 np_thru_hole circle (at 0 0) (size 2.5 2.5) (drill 2.5) (layers *.Cu *.Mask))
)
(module Mounting_Holes:MountingHole_2.5mm (layer F.Cu) (tedit 5C50A659) (tstamp 5C508FD2)
(at 164.7 84.3)
(descr "Mounting Hole 2.5mm, no annular")
(tags "mounting hole 2.5mm no annular")
(attr virtual)
(fp_text reference REF** (at 0 -3.5) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MountingHole_2.5mm (at 0 3.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0.3 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 2.5 0) (layer Cmts.User) (width 0.15))
(fp_circle (center 0 0) (end 2.75 0) (layer F.CrtYd) (width 0.05))
(pad 1 np_thru_hole circle (at 0 0) (size 2.5 2.5) (drill 2.5) (layers *.Cu *.Mask))
)
(module Symbols:OSHW-Logo_5.7x6mm_SilkScreen (layer B.Cu) (tedit 0) (tstamp 5C515B0D)
(at 131.6 109.3 180)
(descr "Open Source Hardware Logo")
(tags "Logo OSHW")
(attr virtual)
(fp_text reference REF*** (at 0 0 180) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value OSHW-Logo_5.7x6mm_SilkScreen (at 0.75 0 180) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_poly (pts (xy -1.908759 -1.469184) (xy -1.882247 -1.482282) (xy -1.849553 -1.505106) (xy -1.825725 -1.529996)
(xy -1.809406 -1.561249) (xy -1.79924 -1.603166) (xy -1.793872 -1.660044) (xy -1.791944 -1.736184)
(xy -1.791831 -1.768917) (xy -1.792161 -1.840656) (xy -1.793527 -1.891927) (xy -1.7965 -1.927404)
(xy -1.801649 -1.951763) (xy -1.809543 -1.96968) (xy -1.817757 -1.981902) (xy -1.870187 -2.033905)
(xy -1.93193 -2.065184) (xy -1.998536 -2.074592) (xy -2.065558 -2.06098) (xy -2.086792 -2.051354)
(xy -2.137624 -2.024859) (xy -2.137624 -2.440052) (xy -2.100525 -2.420868) (xy -2.051643 -2.406025)
(xy -1.991561 -2.402222) (xy -1.931564 -2.409243) (xy -1.886256 -2.425013) (xy -1.848675 -2.455047)
(xy -1.816564 -2.498024) (xy -1.81415 -2.502436) (xy -1.803967 -2.523221) (xy -1.79653 -2.54417)
(xy -1.791411 -2.569548) (xy -1.788181 -2.603618) (xy -1.786413 -2.650641) (xy -1.785677 -2.714882)
(xy -1.785544 -2.787176) (xy -1.785544 -3.017822) (xy -1.923861 -3.017822) (xy -1.923861 -2.592533)
(xy -1.962549 -2.559979) (xy -2.002738 -2.53394) (xy -2.040797 -2.529205) (xy -2.079066 -2.541389)
(xy -2.099462 -2.55332) (xy -2.114642 -2.570313) (xy -2.125438 -2.595995) (xy -2.132683 -2.633991)
(xy -2.137208 -2.687926) (xy -2.139844 -2.761425) (xy -2.140772 -2.810347) (xy -2.143911 -3.011535)
(xy -2.209926 -3.015336) (xy -2.27594 -3.019136) (xy -2.27594 -1.77065) (xy -2.137624 -1.77065)
(xy -2.134097 -1.840254) (xy -2.122215 -1.888569) (xy -2.10002 -1.918631) (xy -2.065559 -1.933471)
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(xy -0.749984 -0.761599) (xy -0.774417 -0.74865) (xy -0.878178 -0.692547) (xy -1.001787 -0.776155)
(xy -1.064886 -0.818987) (xy -1.13397 -0.866122) (xy -1.198707 -0.910503) (xy -1.231134 -0.932852)
(xy -1.276741 -0.963477) (xy -1.31536 -0.987747) (xy -1.341952 -1.002587) (xy -1.35059 -1.005724)
(xy -1.363161 -0.997261) (xy -1.390984 -0.973636) (xy -1.431361 -0.937302) (xy -1.481595 -0.890711)
(xy -1.538988 -0.836317) (xy -1.575286 -0.801392) (xy -1.63879 -0.738996) (xy -1.693673 -0.683188)
(xy -1.737714 -0.636354) (xy -1.768695 -0.600882) (xy -1.784398 -0.579161) (xy -1.785905 -0.574752)
(xy -1.778914 -0.557985) (xy -1.759594 -0.524082) (xy -1.730091 -0.476476) (xy -1.692545 -0.418599)
(xy -1.6491 -0.353884) (xy -1.636745 -0.335842) (xy -1.591727 -0.270267) (xy -1.55134 -0.211228)
(xy -1.51784 -0.162042) (xy -1.493486 -0.126028) (xy -1.480536 -0.106502) (xy -1.479285 -0.104483)
(xy -1.481156 -0.088922) (xy -1.491087 -0.054709) (xy -1.507347 -0.006355) (xy -1.528205 0.051629)
(xy -1.551927 0.11473) (xy -1.576784 0.178437) (xy -1.601042 0.238239) (xy -1.622971 0.289624)
(xy -1.640838 0.328081) (xy -1.652913 0.349098) (xy -1.653771 0.350106) (xy -1.661154 0.356112)
(xy -1.673625 0.362052) (xy -1.69392 0.36854) (xy -1.724778 0.376191) (xy -1.768934 0.38562)
(xy -1.829126 0.397441) (xy -1.908093 0.412271) (xy -2.00857 0.430723) (xy -2.030325 0.43469)
(xy -2.094802 0.447147) (xy -2.151011 0.459334) (xy -2.193987 0.470074) (xy -2.21876 0.478191)
(xy -2.222082 0.480084) (xy -2.227556 0.496862) (xy -2.232006 0.534355) (xy -2.235428 0.588206)
(xy -2.237819 0.654056) (xy -2.239177 0.727547) (xy -2.239499 0.80432) (xy -2.238781 0.880017)
(xy -2.237021 0.95028) (xy -2.234216 1.01075) (xy -2.230362 1.05707) (xy -2.225457 1.084881)
(xy -2.2225 1.090573) (xy -2.206037 1.096314) (xy -2.168551 1.105655) (xy -2.113775 1.117785)
(xy -2.045445 1.131893) (xy -1.967294 1.14717) (xy -1.924716 1.155177) (xy -1.843929 1.170279)
(xy -1.771887 1.18396) (xy -1.712111 1.195533) (xy -1.668121 1.204313) (xy -1.643439 1.209613)
(xy -1.639377 1.210788) (xy -1.632511 1.224035) (xy -1.617998 1.255943) (xy -1.597771 1.301953)
(xy -1.573766 1.357508) (xy -1.547918 1.418047) (xy -1.52216 1.479014) (xy -1.498427 1.535849)
(xy -1.478654 1.583994) (xy -1.464776 1.61889) (xy -1.458726 1.635979) (xy -1.458614 1.636726)
(xy -1.465472 1.650207) (xy -1.484698 1.68123) (xy -1.514272 1.726711) (xy -1.552173 1.783568)
(xy -1.59638 1.848717) (xy -1.622079 1.886138) (xy -1.668907 1.954753) (xy -1.710499 2.017048)
(xy -1.744825 2.069871) (xy -1.769857 2.110073) (xy -1.783565 2.1345) (xy -1.785544 2.139976)
(xy -1.777034 2.152722) (xy -1.753507 2.179937) (xy -1.717968 2.218572) (xy -1.673423 2.265577)
(xy -1.622877 2.317905) (xy -1.569336 2.372505) (xy -1.515805 2.42633) (xy -1.465289 2.47633)
(xy -1.420794 2.519457) (xy -1.385325 2.552661) (xy -1.361887 2.572894) (xy -1.354046 2.577722)
(xy -1.34128 2.570933) (xy -1.310744 2.551858) (xy -1.26541 2.522439) (xy -1.208244 2.484619)
(xy -1.142216 2.440339) (xy -1.09241 2.406605) (xy -0.840764 2.235488) (xy -0.631001 2.321959)
(xy -0.421237 2.40843) (xy -0.364389 2.709982) (xy -0.30754 3.011534) (xy 0.320115 3.011534)
(xy 0.376964 2.709982)) (layer B.SilkS) (width 0.01))
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(module Capacitors_SMD:C_0603_1608Metric (layer B.Cu) (tedit 5C58C5EF) (tstamp 5C58F375)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(at 143.51 102.87 90)
(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags capacitor)
(path /5C576327)
(attr smd)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(fp_text reference C2 (at 0 1.27 90) (layer B.SilkS)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.43 90) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -1.48 -0.73) (end -1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end 1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end 1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end -1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 90) (layer B.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)) (justify mirror))
)
(pad 1 smd roundrect (at -0.7875 0 90) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 2 smd roundrect (at 0.7875 0 90) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 9 ANEMOMETER))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_1608Metric (layer B.Cu) (tedit 5C570510) (tstamp 5C5A1D7C)
(at 146.05 100.33)
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5C57FF00)
(attr smd)
(fp_text reference R4 (at 0 1.43) (layer B.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100k (at 0 -1.43) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -1.48 -0.73) (end -1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end 1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end 1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end -1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer B.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)) (justify mirror))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 1 5V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 14 "Net-(R1-Pad2)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(module Resistors_SMD:R_0603_1608Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5C5E8343)
(at 142.24 110.49 270)
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5C58EB09)
(attr smd)
(fp_text reference R5 (at 0 -3.175 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k (at 0 -1.43 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -1.48 -0.73) (end -1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end 1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end 1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end -1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer B.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)) (justify mirror))
)
(pad 1 smd roundrect (at -0.7875 0 270) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 25 NCHRG))
(pad 2 smd roundrect (at 0.7875 0 270) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 20 BAT_CHARGING))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(module Resistors_SMD:R_0603_1608Metric (layer B.Cu) (tedit 5B301BBD) (tstamp 5C5E8354)
(at 140.97 110.49 270)
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5C58EB15)
(attr smd)
(fp_text reference R6 (at 0 -3.175 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k (at 0 -1.43 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user %R (at 0 0 270) (layer B.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)) (justify mirror))
)
(fp_line (start 1.48 -0.73) (end -1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end 1.48 -0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end 1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end -1.48 0.73) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer B.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer B.SilkS) (width 0.12))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 270) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 21 BAT_CHARGED))
(pad 1 smd roundrect (at -0.7875 0 270) (size 0.875 0.95) (layers B.Cu B.Paste B.Mask) (roundrect_rratio 0.25)
(net 26 NSTBY))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(module TestPoint:TestPoint_THTPad_1.5x1.5mm_Drill0.7mm (layer B.Cu) (tedit 5C58C0C0) (tstamp 5C58CF0C)
(at 140.97 104.775)
(descr "THT rectangular pad as test Point, square 1.5mm side length, hole diameter 0.7mm")
(tags "test point THT pad rectangle square")
(path /5C5715CF)
(attr virtual)
(fp_text reference CHRG (at 3.175 0.635) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value BAT_CHARGING (at 0 -1.75) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user %R (at 0 1.65) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.95 0.95) (end 0.95 0.95) (layer B.SilkS) (width 0.12))
(fp_line (start 0.95 0.95) (end 0.95 -0.95) (layer B.SilkS) (width 0.12))
(fp_line (start 0.95 -0.95) (end -0.95 -0.95) (layer B.SilkS) (width 0.12))
(fp_line (start -0.95 -0.95) (end -0.95 0.95) (layer B.SilkS) (width 0.12))
(fp_line (start -1.25 1.25) (end 1.25 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.25 1.25) (end -1.25 -1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.25 -1.25) (end 1.25 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.25 -1.25) (end -1.25 -1.25) (layer B.CrtYd) (width 0.05))
(pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 0.7) (layers *.Cu *.Mask)
(net 25 NCHRG))
)
(module TestPoint:TestPoint_THTPad_1.5x1.5mm_Drill0.7mm (layer B.Cu) (tedit 5C58C0E6) (tstamp 5C5E8894)
(at 140.97 107.315)
(descr "THT rectangular pad as test Point, square 1.5mm side length, hole diameter 0.7mm")
(tags "test point THT pad rectangle square")
(path /5C57277C)
(attr virtual)
(fp_text reference FULL (at 3.175 0) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value BAT_CHARGED (at 0 -1.75) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.25 -1.25) (end -1.25 -1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.25 -1.25) (end 1.25 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.25 1.25) (end -1.25 -1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.25 1.25) (end 1.25 1.25) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.95 -0.95) (end -0.95 0.95) (layer B.SilkS) (width 0.12))
(fp_line (start 0.95 -0.95) (end -0.95 -0.95) (layer B.SilkS) (width 0.12))
(fp_line (start 0.95 0.95) (end 0.95 -0.95) (layer B.SilkS) (width 0.12))
(fp_line (start -0.95 0.95) (end 0.95 0.95) (layer B.SilkS) (width 0.12))
(fp_text user %R (at 0 1.65) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 0.7) (layers *.Cu *.Mask)
(net 26 NSTBY))
)
(module TestPoint:TestPoint_THTPad_1.5x1.5mm_Drill0.7mm (layer F.Cu) (tedit 5C58C54A) (tstamp 5C58C310)
(at 168.91 83.82)
(descr "THT rectangular pad as test Point, square 1.5mm side length, hole diameter 0.7mm")
(tags "test point THT pad rectangle square")
(path /5C573A1A)
(attr virtual)
(fp_text reference D3 (at 0 1.905) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value GPIO3 (at 0 1.75) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 -1.65) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.95 -0.95) (end 0.95 -0.95) (layer F.SilkS) (width 0.12))
(fp_line (start 0.95 -0.95) (end 0.95 0.95) (layer F.SilkS) (width 0.12))
(fp_line (start 0.95 0.95) (end -0.95 0.95) (layer F.SilkS) (width 0.12))
(fp_line (start -0.95 0.95) (end -0.95 -0.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.25 -1.25) (end 1.25 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -1.25) (end -1.25 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.25 1.25) (end 1.25 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.25 1.25) (end -1.25 1.25) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 0.7) (layers *.Cu *.Mask)
(net 22 GPIO3))
)
(module TestPoint:TestPoint_THTPad_1.5x1.5mm_Drill0.7mm (layer F.Cu) (tedit 5C58C55A) (tstamp 5C58EB25)
(at 171.45 83.82)
(descr "THT rectangular pad as test Point, square 1.5mm side length, hole diameter 0.7mm")
(tags "test point THT pad rectangle square")
(path /5C574DB6)
(attr virtual)
(fp_text reference D4 (at 0 1.905) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value GPIO4 (at 0 1.75) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.25 1.25) (end -1.25 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.25 1.25) (end 1.25 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -1.25) (end -1.25 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -1.25) (end 1.25 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.95 0.95) (end -0.95 -0.95) (layer F.SilkS) (width 0.12))
(fp_line (start 0.95 0.95) (end -0.95 0.95) (layer F.SilkS) (width 0.12))
(fp_line (start 0.95 -0.95) (end 0.95 0.95) (layer F.SilkS) (width 0.12))
(fp_line (start -0.95 -0.95) (end 0.95 -0.95) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 0 -1.65) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 0.7) (layers *.Cu *.Mask)
(net 23 GPIO4))
)
(module TestPoint:TestPoint_THTPad_1.5x1.5mm_Drill0.7mm (layer F.Cu) (tedit 5C58C53B) (tstamp 5C58F007)
(at 172.72 110.49)
(descr "THT rectangular pad as test Point, square 1.5mm side length, hole diameter 0.7mm")
(tags "test point THT pad rectangle square")
(path /5C576251)
(attr virtual)
(fp_text reference D8 (at 0 1.905) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value GPIO8 (at 0 1.75) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 -1.65) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.95 -0.95) (end 0.95 -0.95) (layer F.SilkS) (width 0.12))
(fp_line (start 0.95 -0.95) (end 0.95 0.95) (layer F.SilkS) (width 0.12))
(fp_line (start 0.95 0.95) (end -0.95 0.95) (layer F.SilkS) (width 0.12))
(fp_line (start -0.95 0.95) (end -0.95 -0.95) (layer F.SilkS) (width 0.12))
(fp_line (start -1.25 -1.25) (end 1.25 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -1.25) (end -1.25 1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.25 1.25) (end 1.25 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.25 1.25) (end -1.25 1.25) (layer F.CrtYd) (width 0.05))
(pad 1 thru_hole rect (at 0 0) (size 1.5 1.5) (drill 0.7) (layers *.Cu *.Mask)
(net 24 GPIO8))
)
(module Resistors_THT:R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal (layer B.Cu) (tedit 5C58BFD6) (tstamp 5C58C5FC)
(at 141.8 99.9)
(descr "Resistor, Axial_DIN0207 series, Axial, Horizontal, pin pitch=7.62mm, 0.25W = 1/4W, length*diameter=6.3*2.5mm^2, http://cdn-reichelt.de/documents/datenblatt/B400/1_4W%23YAG.pdf")
(tags "Resistor Axial_DIN0207 series Axial Horizontal pin pitch 7.62mm 0.25W = 1/4W length 6.3mm diameter 2.5mm")
(path /5C36B93E)
(fp_text reference R1 (at 1.075 -2.11) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100k (at 3.81 -2.37) (layer B.Fab) hide
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.66 1.25) (end 0.66 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0.66 -1.25) (end 6.96 -1.25) (layer B.Fab) (width 0.1))
(fp_line (start 6.96 -1.25) (end 6.96 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 6.96 1.25) (end 0.66 1.25) (layer B.Fab) (width 0.1))
(fp_line (start 0 0) (end 0.66 0) (layer B.Fab) (width 0.1))
(fp_line (start 7.62 0) (end 6.96 0) (layer B.Fab) (width 0.1))
(fp_line (start 0.54 1.04) (end 0.54 1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 0.54 1.37) (end 7.08 1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 7.08 1.37) (end 7.08 1.04) (layer B.SilkS) (width 0.12))
(fp_line (start 0.54 -1.04) (end 0.54 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 0.54 -1.37) (end 7.08 -1.37) (layer B.SilkS) (width 0.12))
(fp_line (start 7.08 -1.37) (end 7.08 -1.04) (layer B.SilkS) (width 0.12))
(fp_line (start -1.05 1.5) (end -1.05 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.05 -1.5) (end 8.67 -1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 8.67 -1.5) (end 8.67 1.5) (layer B.CrtYd) (width 0.05))
(fp_line (start 8.67 1.5) (end -1.05 1.5) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 0) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole circle (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 1 5V))
(pad 2 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 14 "Net-(R1-Pad2)"))
(model ${KISYS3DMOD}/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(dimension 50 (width 0.3) (layer Dwgs.User)
(gr_text "50.000 mm" (at 153 126.1) (layer Dwgs.User)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(feature1 (pts (xy 128 120) (xy 128 124.586421)))
(feature2 (pts (xy 178 120) (xy 178 124.586421)))
(crossbar (pts (xy 178 124) (xy 128 124)))
(arrow1a (pts (xy 128 124) (xy 129.126504 123.413579)))
(arrow1b (pts (xy 128 124) (xy 129.126504 124.586421)))
(arrow2a (pts (xy 178 124) (xy 176.873496 123.413579)))
(arrow2b (pts (xy 178 124) (xy 176.873496 124.586421)))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text øko (at 131.8 101.2 270) (layer B.SilkS)
(effects (font (size 3 3) (thickness 0.5)) (justify mirror))
)
(gr_line (start 178 113.5) (end 128 113.5) (layer Edge.Cuts) (width 0.001))
(gr_line (start 178 81.5) (end 128 81.5) (layer Edge.Cuts) (width 0.001))
(dimension 16 (width 0.3) (layer Dwgs.User)
(gr_text "16.000 mm" (at 117.9 105.3 90) (layer Dwgs.User)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(feature1 (pts (xy 113.9 97.3) (xy 116.386421 97.3)))
(feature2 (pts (xy 113.9 113.3) (xy 116.386421 113.3)))
(crossbar (pts (xy 115.8 113.3) (xy 115.8 97.3)))
(arrow1a (pts (xy 115.8 97.3) (xy 116.386421 98.426504)))
(arrow1b (pts (xy 115.8 97.3) (xy 115.213579 98.426504)))
(arrow2a (pts (xy 115.8 113.3) (xy 116.386421 112.173496)))
(arrow2b (pts (xy 115.8 113.3) (xy 115.213579 112.173496)))
)
(dimension 10 (width 0.3) (layer Dwgs.User)
(gr_text "10.000 mm" (at 159.9 74.8) (layer Dwgs.User)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(feature1 (pts (xy 164.9 78.9) (xy 164.9 76.313579)))
(feature2 (pts (xy 154.9 78.9) (xy 154.9 76.313579)))
(crossbar (pts (xy 154.9 76.9) (xy 164.9 76.9)))
(arrow1a (pts (xy 164.9 76.9) (xy 163.773496 77.486421)))
(arrow1b (pts (xy 164.9 76.9) (xy 163.773496 76.313579)))
(arrow2a (pts (xy 154.9 76.9) (xy 156.026504 77.486421)))
(arrow2b (pts (xy 154.9 76.9) (xy 156.026504 76.313579)))
)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(gr_text OUT+ (at 146 95.2) (layer B.SilkS) (tstamp 5C3A792E)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text B+ (at 147.1 96.7) (layer B.SilkS) (tstamp 5C3A7894)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(gr_text OUT- (at 146.05 108.585) (layer B.SilkS) (tstamp 5C3A77FA)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(gr_text B- (at 147.2 106) (layer B.SilkS) (tstamp 5C3A7760)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(gr_text "2019 okoyono.de" (at 148.7 112.2) (layer B.SilkS)
(effects (font (size 0.7 0.7) (thickness 0.15)) (justify left mirror))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_line (start 173.9 88.4) (end 174.2 88.7) (layer B.SilkS) (width 0.2))
(gr_line (start 173.6 88.7) (end 173.9 88.4) (layer B.SilkS) (width 0.2))
(gr_line (start 173.9 88.6) (end 173.9 88.4) (layer B.SilkS) (width 0.2))
(gr_line (start 173.9 91) (end 173.9 88.6) (layer B.SilkS) (width 0.2))
(gr_line (start 169.7 91.1) (end 173.9 91.1) (layer B.SilkS) (width 0.2))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(gr_text "Bridged: DeepSleep mode\nOpen: Flash firmware" (at 169.5 91.1) (layer B.SilkS)
(effects (font (size 0.7 0.7) (thickness 0.15)) (justify left mirror))
)
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(gr_text "Der Zugang zu Computern und\nallem, was einem zeigen kann,\nwie diese Welt funktioniert, sollte\nunbegrenzt und vollständig sein.\n\nAlle Informationen müssen frei sein.\n\nMißtraue Autoritäten – fördere\nDezentralisierung.\n\nÖffentliche Daten nützen, private\nDaten schützen." (at 172.5 101.3) (layer B.SilkS) (tstamp 5C4D83B0)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 0.7 0.7) (thickness 0.1)) (justify left mirror))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_line (start 134.5 87.3) (end 134.5 93.3) (layer F.SilkS) (width 0.2))
(gr_text WIND (at 141.9 88.9 90) (layer F.SilkS) (tstamp 5C399EEB)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text CELL- (at 139.3 89.4 90) (layer F.SilkS) (tstamp 5C399EE9)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text SOLAR+ (at 135.4 89.9 90) (layer F.SilkS) (tstamp 5C399EE7)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text SOLAR- (at 136.7 89.9 90) (layer F.SilkS) (tstamp 5C399EE5)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text CELL+ (at 138 89.4 90) (layer F.SilkS) (tstamp 5C399EE3)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text WIND (at 140.6 88.9 90) (layer F.SilkS) (tstamp 5C399EE2)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_line (start 148.6 83) (end 148.6 90.4) (layer B.SilkS) (width 0.2))
(gr_line (start 133.3 83) (end 133.3 92.8) (layer B.SilkS) (width 0.2))
(gr_line (start 143.5 82.9) (end 143.5 92.7) (layer B.SilkS) (width 0.2))
(gr_line (start 138.4 83) (end 138.4 92.7) (layer B.SilkS) (width 0.2))
(gr_text SOLAR+ (at 134.6 90 90) (layer B.SilkS) (tstamp 5C398BE8)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text SOLAR- (at 137.1 90 90) (layer B.SilkS) (tstamp 5C398A12)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text CELL+ (at 139.7 89.4 90) (layer B.SilkS) (tstamp 5C3988DA)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text CELL- (at 142.2 89.4 90) (layer B.SilkS)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text WIND (at 144.8 89 90) (layer B.SilkS)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text WIND (at 147.3 89 90) (layer B.SilkS) (tstamp 5C397C17)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(gr_text v.2 (at 174.9 105.9) (layer F.SilkS)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.2)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_text "weather statiøn" (at 168.3 108) (layer F.SilkS)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1.2) (thickness 0.25)))
)
(gr_text øko (at 166.5 104.9) (layer F.SilkS)
(effects (font (size 4 4) (thickness 0.8)))
)
(gr_text BME280 (at 132 90.6 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.2)) (justify mirror))
)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(gr_text ADPS-9960 (at 140.335 97.79 90) (layer B.SilkS)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1 1) (thickness 0.2)) (justify mirror))
)
(gr_text + (at 176.4 88.8) (layer B.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(gr_text - (at 174.625 111.76) (layer B.SilkS)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(dimension 32 (width 0.3) (layer Dwgs.User)
(gr_text "32.000 mm" (at 109.9 97.5 90) (layer Dwgs.User)
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(feature1 (pts (xy 116 81.5) (xy 111.413579 81.5)))
(feature2 (pts (xy 116 113.5) (xy 111.413579 113.5)))
(crossbar (pts (xy 112 113.5) (xy 112 81.5)))
(arrow1a (pts (xy 112 81.5) (xy 112.586421 82.626504)))
(arrow1b (pts (xy 112 81.5) (xy 111.413579 82.626504)))
(arrow2a (pts (xy 112 113.5) (xy 112.586421 112.373496)))
(arrow2b (pts (xy 112 113.5) (xy 111.413579 112.373496)))
)
Change PCB to square
2019-01-30 09:30:51 +01:00
(gr_line (start 178 81.5) (end 178 113.5) (layer Edge.Cuts) (width 0.001) (tstamp 5C50BB01))
(gr_line (start 128 113.5) (end 128 81.5) (layer Edge.Cuts) (width 0.001) (tstamp 5C50BAF5))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 149.05 94.15) (end 149 94.1) (width 0.6) (layer B.Cu) (net 1))
(segment (start 152.85 94.15) (end 149.05 94.15) (width 0.6) (layer B.Cu) (net 1))
(segment (start 154.212 94.15) (end 152.85 94.15) (width 0.6) (layer B.Cu) (net 1))
(segment (start 154.262001 94.200001) (end 154.212 94.15) (width 0.6) (layer B.Cu) (net 1))
(segment (start 163.932791 94.200001) (end 154.262001 94.200001) (width 0.6) (layer B.Cu) (net 1))
(segment (start 168.29 89.842792) (end 163.932791 94.200001) (width 0.6) (layer B.Cu) (net 1))
(segment (start 168.29 88.57) (end 168.29 89.842792) (width 0.6) (layer B.Cu) (net 1))
minor changes
2019-01-27 13:11:12 +01:00
(via (at 140.97 90.3) (size 1.2) (drill 0.5) (layers F.Cu B.Cu) (net 1))
(segment (start 144.77 94.1) (end 140.97 90.3) (width 0.6) (layer B.Cu) (net 1))
(segment (start 147.98 94.1) (end 144.78 94.1) (width 0.6) (layer B.Cu) (net 1))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(segment (start 142 99.6) (end 141.8 99.8) (width 0.25) (layer F.Cu) (net 1))
minor changes
2019-01-27 13:11:12 +01:00
(segment (start 147.98 94.1) (end 149 94.1) (width 0.6) (layer B.Cu) (net 1))
(segment (start 142.24 91.57) (end 140.97 90.3) (width 0.6) (layer F.Cu) (net 1))
(segment (start 142.24 99.73) (end 142.24 91.57) (width 0.6) (layer F.Cu) (net 1))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 142.23 100.33) (end 141.8 99.9) (width 0.25) (layer B.Cu) (net 1))
(segment (start 145.2625 100.33) (end 142.23 100.33) (width 0.25) (layer B.Cu) (net 1))
Fix small silkscreen issues
2019-02-03 20:57:10 +01:00
(via (at 133.35 105.41) (size 1.2) (drill 0.5) (layers F.Cu B.Cu) (net 2) (tstamp 5C5A3AB2))
(via (at 168.91 95.25) (size 1.2) (drill 0.5) (layers F.Cu B.Cu) (net 2) (tstamp 5C59FBA8))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 149.05 108.35) (end 149 108.4) (width 0.6) (layer B.Cu) (net 2))
(segment (start 152.85 108.35) (end 149.05 108.35) (width 0.6) (layer B.Cu) (net 2))
(segment (start 129.96 93.42) (end 131.03763 93.42) (width 0.25) (layer B.Cu) (net 2))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(segment (start 137.96 101.42) (end 137.96 101.8) (width 0.25) (layer F.Cu) (net 3))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 133 96.84) (end 133 93.92) (width 0.25) (layer F.Cu) (net 3))
(segment (start 137.96 101.8) (end 133 96.84) (width 0.25) (layer F.Cu) (net 3))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(segment (start 135.89 96.355486) (end 136.995486 95.25) (width 0.25) (layer B.Cu) (net 3))
(segment (start 137.96 101.8) (end 135.89 99.73) (width 0.25) (layer B.Cu) (net 3))
(segment (start 135.89 99.73) (end 135.89 96.355486) (width 0.25) (layer B.Cu) (net 3))
(segment (start 130.721999 90.118001) (end 129.96 90.88) (width 0.25) (layer F.Cu) (net 3))
(segment (start 155.59 88.57) (end 154.272999 87.252999) (width 0.25) (layer F.Cu) (net 3))
(segment (start 129.96 90.88) (end 133 93.92) (width 0.25) (layer F.Cu) (net 3))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 133.424999 85.035999) (end 135.210988 83.25001) (width 0.25) (layer F.Cu) (net 3))
(segment (start 133.424999 86.483763) (end 133.424999 85.035999) (width 0.25) (layer F.Cu) (net 3))
(segment (start 130.721999 90.118001) (end 130.721999 89.186763) (width 0.25) (layer F.Cu) (net 3))
(segment (start 130.721999 89.186763) (end 133.424999 86.483763) (width 0.25) (layer F.Cu) (net 3))
(segment (start 151.716589 87.252999) (end 154.272999 87.252999) (width 0.25) (layer F.Cu) (net 3))
(segment (start 147.7136 83.25001) (end 151.716589 87.252999) (width 0.25) (layer F.Cu) (net 3))
(segment (start 135.210988 83.25001) (end 147.7136 83.25001) (width 0.25) (layer F.Cu) (net 3))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 137.96 103.96) (end 137.96 104.34) (width 0.25) (layer F.Cu) (net 4))
(segment (start 130.721999 89.101999) (end 129.96 88.34) (width 0.25) (layer B.Cu) (net 4))
(segment (start 135.2 93.58) (end 130.721999 89.101999) (width 0.25) (layer B.Cu) (net 4))
(segment (start 137.96 104.34) (end 135.2 101.58) (width 0.25) (layer B.Cu) (net 4))
minor changes
2019-01-27 13:11:12 +01:00
(segment (start 137.16 93.98) (end 135.764514 93.98) (width 0.25) (layer B.Cu) (net 4))
(segment (start 135.2 101.58) (end 135.2 93.98) (width 0.25) (layer B.Cu) (net 4))
(segment (start 135.764514 93.98) (end 135.2 93.98) (width 0.25) (layer B.Cu) (net 4))
(segment (start 135.2 93.98) (end 135.2 93.58) (width 0.25) (layer B.Cu) (net 4))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 157.230001 87.670001) (end 158.13 88.57) (width 0.25) (layer F.Cu) (net 4))
(segment (start 156.362989 86.802989) (end 157.230001 87.670001) (width 0.25) (layer F.Cu) (net 4))
(segment (start 129.96 88.34) (end 130.721999 87.578001) (width 0.25) (layer F.Cu) (net 4))
(segment (start 130.721999 87.578001) (end 130.721999 86.646763) (width 0.25) (layer F.Cu) (net 4))
(segment (start 130.721999 86.646763) (end 134.568762 82.8) (width 0.25) (layer F.Cu) (net 4))
(segment (start 134.568762 82.8) (end 147.9 82.8) (width 0.25) (layer F.Cu) (net 4))
(segment (start 147.9 82.8) (end 151.902989 86.802989) (width 0.25) (layer F.Cu) (net 4))
(segment (start 151.902989 86.802989) (end 156.362989 86.802989) (width 0.25) (layer F.Cu) (net 4))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 136.872999 105.792999) (end 136.872999 102.872999) (width 0.25) (layer F.Cu) (net 5))
(segment (start 130.721999 96.721999) (end 129.96 95.96) (width 0.25) (layer F.Cu) (net 5))
(segment (start 136.872999 102.872999) (end 130.721999 96.721999) (width 0.25) (layer F.Cu) (net 5))
(segment (start 137.96 106.88) (end 136.872999 105.792999) (width 0.25) (layer F.Cu) (net 5))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(segment (start 138.570486 96.52) (end 138.570486 93.98) (width 0.25) (layer B.Cu) (net 5))
(segment (start 139.047001 96.996515) (end 138.570486 96.52) (width 0.25) (layer B.Cu) (net 5))
(segment (start 137.96 106.88) (end 139.047001 105.792999) (width 0.25) (layer B.Cu) (net 5))
(segment (start 139.047001 105.792999) (end 139.047001 96.996515) (width 0.25) (layer B.Cu) (net 5))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 167.064999 112.655001) (end 168.29 111.43) (width 0.25) (layer F.Cu) (net 5))
(segment (start 136.872999 107.967001) (end 136.872999 110.202999) (width 0.25) (layer F.Cu) (net 5))
(segment (start 137.96 106.88) (end 136.872999 107.967001) (width 0.25) (layer F.Cu) (net 5))
(segment (start 136.872999 110.202999) (end 137.542999 110.872999) (width 0.25) (layer F.Cu) (net 5))
(segment (start 140.595001 112.655001) (end 167.064999 112.655001) (width 0.25) (layer F.Cu) (net 5))
(segment (start 137.542999 110.872999) (end 138.812999 110.872999) (width 0.25) (layer F.Cu) (net 5))
(segment (start 138.812999 110.872999) (end 140.595001 112.655001) (width 0.25) (layer F.Cu) (net 5))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 176.35 91.05) (end 176.4 91) (width 0.6) (layer B.Cu) (net 7))
(segment (start 176.35 94.15) (end 176.35 91.05) (width 0.6) (layer B.Cu) (net 7))
(segment (start 134.6 85.6) (end 138.19949 82.00051) (width 0.6) (layer B.Cu) (net 7))
(segment (start 138.19949 82.00051) (end 147.90051 82.00051) (width 0.6) (layer B.Cu) (net 7))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 147.90051 82.00051) (end 175.98051 82.00051) (width 0.6) (layer B.Cu) (net 7))
(segment (start 176.4 82.42) (end 176.4 91) (width 0.6) (layer B.Cu) (net 7))
(segment (start 175.98051 82.00051) (end 176.4 82.42) (width 0.6) (layer B.Cu) (net 7))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 176.4 108.4) (end 176.35 108.35) (width 0.6) (layer B.Cu) (net 8) (status 30))
(segment (start 176.4 111.7) (end 176.4 108.4) (width 0.6) (layer B.Cu) (net 8) (status 30))
(segment (start 164.450001 97.812001) (end 174.988 108.35) (width 0.6) (layer B.Cu) (net 8))
(segment (start 174.988 108.35) (end 176.35 108.35) (width 0.6) (layer B.Cu) (net 8))
(segment (start 146.652001 97.812001) (end 164.450001 97.812001) (width 0.6) (layer B.Cu) (net 8))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 137.989999 91.489999) (end 141.558606 95.058606) (width 0.6) (layer B.Cu) (net 8))
(segment (start 137.989999 86.449999) (end 137.989999 91.489999) (width 0.6) (layer B.Cu) (net 8))
(segment (start 137.14 85.6) (end 137.989999 86.449999) (width 0.6) (layer B.Cu) (net 8))
(segment (start 145.4 97.812001) (end 144.802001 97.812001) (width 0.6) (layer B.Cu) (net 8))
(segment (start 146.652001 97.812001) (end 145.4 97.812001) (width 0.6) (layer B.Cu) (net 8))
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(segment (start 144.312001 97.812001) (end 141.558606 95.058606) (width 0.6) (layer B.Cu) (net 8))
(segment (start 144.802001 97.812001) (end 144.312001 97.812001) (width 0.6) (layer B.Cu) (net 8))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 163.21 110.157208) (end 165.2 108.167208) (width 0.25) (layer F.Cu) (net 9))
(segment (start 163.21 111.43) (end 163.21 110.157208) (width 0.25) (layer F.Cu) (net 9))
(via (at 163.1 93.3) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 9))
(segment (start 165.2 108.167208) (end 165.2 94.7) (width 0.25) (layer F.Cu) (net 9))
(segment (start 163.1 93.3) (end 163.8 93.3) (width 0.25) (layer F.Cu) (net 9))
(segment (start 163.8 93.3) (end 165.2 94.7) (width 0.25) (layer F.Cu) (net 9))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 144.76 98.76) (end 144.76 85.6) (width 0.25) (layer F.Cu) (net 9))
(segment (start 149.1 103.1) (end 144.76 98.76) (width 0.25) (layer F.Cu) (net 9))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 162.700001 92.900001) (end 163.1 93.3) (width 0.25) (layer B.Cu) (net 9))
(segment (start 146.1 92.9) (end 162.700001 92.900001) (width 0.25) (layer B.Cu) (net 9))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 144.76 85.6) (end 144.76 91.56) (width 0.25) (layer B.Cu) (net 9))
(segment (start 144.76 91.56) (end 146.1 92.9) (width 0.25) (layer B.Cu) (net 9))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 143.971612 101.620888) (end 143.51 102.0825) (width 0.25) (layer B.Cu) (net 9))
(segment (start 143.9925 101.6) (end 143.971612 101.620888) (width 0.25) (layer B.Cu) (net 9))
(segment (start 147.6 101.6) (end 143.9925 101.6) (width 0.25) (layer B.Cu) (net 9))
(segment (start 149.1 103.1) (end 147.6 101.6) (width 0.25) (layer B.Cu) (net 9))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 170.96 101.84) (end 170.96 86.9) (width 0.25) (layer F.Cu) (net 10))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 170.96 86.9) (end 173.9 83.96) (width 0.25) (layer F.Cu) (net 10))
(segment (start 162.383 104) (end 167.64 104) (width 0.25) (layer B.Cu) (net 10))
(segment (start 151.735001 110.204999) (end 156.178001 110.204999) (width 0.25) (layer B.Cu) (net 10))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 168.8 104) (end 170.96 101.84) (width 0.25) (layer F.Cu) (net 10))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 167.64 104) (end 168.8 104) (width 0.25) (layer F.Cu) (net 10))
(via (at 167.64 104) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 10))
(segment (start 150.51 111.43) (end 151.735001 110.204999) (width 0.25) (layer B.Cu) (net 10))
(segment (start 156.178001 110.204999) (end 162.383 104) (width 0.25) (layer B.Cu) (net 10))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(via (at 168.91 105.2) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 11))
(segment (start 161.82 105.2) (end 168.91 105.2) (width 0.25) (layer B.Cu) (net 11))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 155.59 111.43) (end 161.82 105.2) (width 0.25) (layer B.Cu) (net 11))
(segment (start 171.45 103.75) (end 171.45 87.85) (width 0.25) (layer F.Cu) (net 11))
(segment (start 172.8 86.5) (end 173.9 86.5) (width 0.25) (layer F.Cu) (net 11))
(segment (start 171.45 87.85) (end 172.8 86.5) (width 0.25) (layer F.Cu) (net 11))
(segment (start 170 105.2) (end 171.45 103.75) (width 0.25) (layer F.Cu) (net 11))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(segment (start 168.91 105.2) (end 170 105.2) (width 0.25) (layer F.Cu) (net 11))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 149.55 96.55) (end 149.5 96.5) (width 0.6) (layer B.Cu) (net 12) (status 30))
(segment (start 152.85 96.55) (end 149.55 96.55) (width 0.6) (layer B.Cu) (net 12) (status 30))
(segment (start 146.677919 96.5) (end 149.5 96.5) (width 0.6) (layer B.Cu) (net 12) (status 20))
minor changes
2019-01-27 13:11:12 +01:00
(segment (start 146.677919 96.5) (end 144.8 96.5) (width 0.6) (layer B.Cu) (net 12))
(segment (start 144.8 96.5) (end 144.76 96.5) (width 0.25) (layer B.Cu) (net 12))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 139.68 91.38) (end 144.8 96.5) (width 0.6) (layer B.Cu) (net 12))
(segment (start 139.68 85.6) (end 139.68 91.38) (width 0.6) (layer B.Cu) (net 12))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 149.55 105.95) (end 149.5 106) (width 0.6) (layer B.Cu) (net 13) (status 30))
(segment (start 152.85 105.95) (end 149.55 105.95) (width 0.6) (layer B.Cu) (net 13) (status 30))
minor changes
2019-01-27 13:11:12 +01:00
(via (at 146.3 105.9) (size 1.2) (drill 0.5) (layers F.Cu B.Cu) (net 13))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 149.4 105.9) (end 149.5 106) (width 0.6) (layer B.Cu) (net 13))
(segment (start 146.3 105.9) (end 149.4 105.9) (width 0.6) (layer B.Cu) (net 13))
minor changes
2019-01-27 13:11:12 +01:00
(segment (start 143.51 89.59) (end 143.51 102.87) (width 0.6) (layer F.Cu) (net 13))
(segment (start 143.51 89.59) (end 142.42 88.5) (width 0.6) (layer F.Cu) (net 13))
(segment (start 143.51 102.87) (end 143.51 103.11) (width 0.25) (layer F.Cu) (net 13))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 142.22 88.3) (end 143.51 89.59) (width 0.6) (layer F.Cu) (net 13))
(segment (start 142.22 85.6) (end 142.22 88.3) (width 0.6) (layer F.Cu) (net 13))
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(segment (start 143.51 103.11) (end 146.3 105.9) (width 0.6) (layer F.Cu) (net 13))
(segment (start 145.900001 105.500001) (end 146.3 105.9) (width 0.6) (layer F.Cu) (net 13))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(via (at 155.3 106.68) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 14))
Finish the pcb design (hopefully)
2019-01-13 00:42:47 +01:00
(segment (start 153.05 111.05) (end 153.05 111.43) (width 0.25) (layer F.Cu) (net 14))
(segment (start 155.3 108.8) (end 153.05 111.05) (width 0.25) (layer F.Cu) (net 14))
changing some tracks, using GND plane
2019-01-27 12:29:51 +01:00
(segment (start 155.3 108.8) (end 155.3 106.68) (width 0.25) (layer F.Cu) (net 14))
minor changes
2019-01-27 13:11:12 +01:00
(segment (start 155.3 106.68) (end 155.3 102.5) (width 0.25) (layer B.Cu) (net 14))
Change PCB to square
2019-01-30 09:30:51 +01:00
(segment (start 149.42 99.9) (end 152.7 99.9) (width 0.25) (layer B.Cu) (net 14))
(segment (start 152.7 99.9) (end 153.4 100.6) (width 0.25) (layer B.Cu) (net 14))
(segment (start 155.3 102.5) (end 153.4 100.6) (width 0.25) (layer B.Cu) (net 14))
(segment (start 153.4 100.6) (end 153.13 100.33) (width 0.25) (layer B.Cu) (net 14))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 147.2675 99.9) (end 146.8375 100.33) (width 0.25) (layer B.Cu) (net 14))
(segment (start 149.42 99.9) (end 147.2675 99.9) (width 0.25) (layer B.Cu) (net 14))
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(segment (start 143.770001 112.655001) (end 142.24 111.125) (width 0.25) (layer B.Cu) (net 20))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 158.13 111.43) (end 156.904999 112.655001) (width 0.25) (layer B.Cu) (net 20))
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(segment (start 156.904999 112.655001) (end 143.770001 112.655001) (width 0.25) (layer B.Cu) (net 20))
(segment (start 140.97 112.395) (end 140.97 111.2775) (width 0.25) (layer B.Cu) (net 21))
(segment (start 141.680011 113.105011) (end 140.97 112.395) (width 0.25) (layer B.Cu) (net 21))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 160.67 111.43) (end 158.994989 113.105011) (width 0.25) (layer B.Cu) (net 21))
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(segment (start 158.994989 113.105011) (end 141.680011 113.105011) (width 0.25) (layer B.Cu) (net 21))
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(segment (start 162.345011 86.894989) (end 168.375011 86.894989) (width 0.25) (layer B.Cu) (net 22))
(segment (start 160.67 88.57) (end 162.345011 86.894989) (width 0.25) (layer B.Cu) (net 22))
(segment (start 168.91 84.82) (end 168.91 83.82) (width 0.25) (layer B.Cu) (net 22))
(segment (start 168.91 86.36) (end 168.91 84.82) (width 0.25) (layer B.Cu) (net 22))
(segment (start 168.375011 86.894989) (end 168.91 86.36) (width 0.25) (layer B.Cu) (net 22))
(segment (start 171.45 84.82) (end 171.45 83.82) (width 0.25) (layer B.Cu) (net 23))
(segment (start 168.925001 87.344999) (end 171.45 84.82) (width 0.25) (layer B.Cu) (net 23))
(segment (start 164.435001 87.344999) (end 168.925001 87.344999) (width 0.25) (layer B.Cu) (net 23))
(segment (start 163.21 88.57) (end 164.435001 87.344999) (width 0.25) (layer B.Cu) (net 23))
(segment (start 166.975001 112.655001) (end 171.824999 112.655001) (width 0.25) (layer B.Cu) (net 24))
(segment (start 165.75 111.43) (end 166.975001 112.655001) (width 0.25) (layer B.Cu) (net 24))
(segment (start 172.72 111.76) (end 172.72 110.49) (width 0.25) (layer B.Cu) (net 24))
(segment (start 171.824999 112.655001) (end 172.72 111.76) (width 0.25) (layer B.Cu) (net 24))
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(segment (start 141.97 104.775) (end 140.97 104.775) (width 0.25) (layer B.Cu) (net 25))
(segment (start 142.24 105.045) (end 141.97 104.775) (width 0.25) (layer B.Cu) (net 25))
(segment (start 142.24 109.7025) (end 142.24 105.045) (width 0.25) (layer B.Cu) (net 25))
(segment (start 140.97 108.4325) (end 140.97 109.7025) (width 0.25) (layer B.Cu) (net 26))
(segment (start 140.97 108.4325) (end 140.97 107.315) (width 0.25) (layer B.Cu) (net 26))
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(zone (net 2) (net_name GND) (layer B.Cu) (tstamp 5C5A56A1) (hatch edge 0.508)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(xy 177.8 81.28) (xy 177.8 113.03) (xy 128.27 113.03) (xy 128.27 81.28)
Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
)
)
(filled_polygon
(pts
Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
(xy 134.44 93.894802) (xy 134.44 93.905148) (xy 134.425111 93.98) (xy 134.440001 94.054857) (xy 134.44 101.505153)
(xy 134.425112 101.58) (xy 134.44 101.654847) (xy 134.44 101.654851) (xy 134.484096 101.876536) (xy 134.652071 102.127929)
(xy 134.71553 102.170331) (xy 136.57598 104.030782) (xy 136.563 104.062119) (xy 136.563 104.617881) (xy 136.77568 105.131337)
(xy 137.168663 105.52432) (xy 137.375513 105.61) (xy 137.168663 105.69568) (xy 136.77568 106.088663) (xy 136.563 106.602119)
(xy 136.563 107.157881) (xy 136.77568 107.671337) (xy 137.168663 108.06432) (xy 137.359647 108.143428) (xy 137.228857 108.197603)
(xy 137.159392 108.439787) (xy 137.96 109.240395) (xy 138.760608 108.439787) (xy 138.691143 108.197603) (xy 138.550607 108.147465)
(xy 138.751337 108.06432) (xy 139.14432 107.671337) (xy 139.357 107.157881) (xy 139.357 106.602119) (xy 139.34402 106.570782)
adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
(xy 139.531474 106.383328) (xy 139.59493 106.340928) (xy 139.762905 106.089536) (xy 139.78156 105.995751) (xy 139.855266 106.045)
(xy 139.762191 106.107191) (xy 139.621843 106.317235) (xy 139.57256 106.565) (xy 139.57256 108.065) (xy 139.621843 108.312765)
(xy 139.762191 108.522809) (xy 139.972235 108.663157) (xy 140.21 108.710451) (xy 140.21 108.798604) (xy 140.101261 108.871261)
(xy 139.913495 109.152273) (xy 139.84756 109.48375) (xy 139.84756 109.92125) (xy 139.913495 110.252727) (xy 140.072036 110.49)
(xy 139.913495 110.727273) (xy 139.84756 111.05875) (xy 139.84756 111.49625) (xy 139.913495 111.827727) (xy 140.101261 112.108739)
(xy 140.21 112.181396) (xy 140.21 112.320153) (xy 140.195112 112.395) (xy 140.21 112.469847) (xy 140.21 112.469851)
(xy 140.254096 112.691536) (xy 140.369667 112.8645) (xy 139.031157 112.8645) (xy 139.14432 112.751337) (xy 139.357 112.237881)
(xy 139.357 111.682119) (xy 139.14432 111.168663) (xy 138.751337 110.77568) (xy 138.560353 110.696572) (xy 138.691143 110.642397)
(xy 138.760608 110.400213) (xy 137.96 109.599605) (xy 137.159392 110.400213) (xy 137.228857 110.642397) (xy 137.369393 110.692535)
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Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
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adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
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Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
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Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
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Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
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Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
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Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
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Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
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Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
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adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
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Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
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Change PCB to square
2019-01-30 09:30:51 +01:00
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adding series resistors to bat status, minor changes
2019-02-05 00:10:58 +01:00
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Adding spare GPIOs, pads for charge status
2019-02-03 17:01:49 +01:00
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Make a nice PCB to hold the components on the board
2019-01-10 22:00:49 +01:00
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